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AN32055A page 1 of 96 product standards typical application features description 7 x 7 dots matrix led driver lsi with step-up dc/dc converter for white led AN32055A is a 6-ch led driver for lcd backlights, and a driver for led matrix. they supply voltage by step-up dc/dc converter. ? 7 x 7 led matrix driver (total led that can be driven = 49) ? built-in memory (rom and ram) ? step-up dc/dc converter ? ldo : 2-ch ? gpio : 2-ch ? gpi : 3-ch (3pins from gpi1 to gpi3 are in common with spi2) ? gpo : 2-ch ? spi interface : 2-ch (spi2 is only receiving. it is possible to control only address 05h by spi2.) ? driver for led (main led : 4-ch, sub led : 2-ch, led for photo flash : 2-ch, rgb color unit : 1-ch) ? 80 pin wafer level chip size package (wlcsp) applications x0~x6 lx vb vbled vbdcdc y0~y6 ldo2 battery int test1 test2 ledgnd1 ledgnd2 rgbgnd1 rgbgnd2 pgnd1 pgnd2 agnd dgnd vibctl 1.0 ? f 22 ? f 4.7 ? h gpi [ 3ch ] di do extclk rstb 27 k ? 100 ? csb clk ledctl b2 g2 r2 dcdcgnd fb vled1 vled2 iref chggnd 10 ? f 0.3 ? gpo [ 2ch ] gpio [ 2ch ] bls [ 2ch ] b1 g1 r1 7 7 ldocnt ledcnt bl [ 4ch ] pl [ 2ch ] 2 4 2 led ldo1 1.0 ? f vrefd 1.0 ? f cpu i/f http://www.semicon. panasonic.co.jp/en/ ? mobile phone ? smart phone ? pcs ? game consoles ? home appliances etc. note) the application circuit is an example. the operation of the mass production set is not guaranteed. sufficient evaluation and verification is required in the design of the mass production set. the customer is fully responsible for the incorporation of t he above illustrated application circuit in the design of the equipment. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 2 of 96 product standards contents ? features ??????????????????????????????? 1 ? description ??..??????????????????????????? 1 ? applications ????????????????????????????? 1 ? typical application ????????????????????????? 1 ? contents ??????????????????????????????? 2 ? absolute maximum ratings ????????????????????? 3 ? power dissipation rating ?????????????????????? 3 ? recommended operating conditions ?..?????????????? 4 ? electrical characteristics .???????????????????? 5 ? pin configuration ????????????????????????..?. 20 ? pin functions .???????????????????????????? 21 ? functional block diagram ..???????????????????? 25 ? operation ?????????????????????????????? 26 ? package information ???????????????????????.. 95 ? important notice ?????????????????????????.... 96 d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 3 of 96 product standards absolute maximum ratings ? v ? 0.3 to 6.5 bl1, bl2, bl3, bl4, bls1, bls2, pl1, pl2, r1, g1, b1, r2, g2, b2, ldo1, ldo2, lx, x0, x1, x2, x3, x4, x5, x6, y0, y1, y2, y3, y4, y5, y6 ? v ? 0.3 to 6.0 ldo1, ldo2 ? v ? 0.3 to 6.0 ledcnt, ldocnt, fb *1 v 6.5 vled max ? v ? 0.3 to 3.4 gpo1, gpo2, int, do output voltage range *2 ? c ? 30 to + 125 t j operating junction temperature ? v ? 0.3 to 3.4 ledctl, rstb, csb, clk, di, extclk, vibctl, gpi1, gpi2, gpi3, gpio1, gpio2 input voltage range *2 ? c ?55to+125 t stg storage temperature ? kv 1.0to1.5 hbm esd note unit rating symbol parameter *2 ? c ?30 to + 85 t opr operating ambience temperature *1 v 6.0 vb max supply voltage 0.335 w 0.837 w 119.4 ? c /w 80 pin wafer level chip size package (wlcsp) p d (ta=85 ? c) p d (ta=25 ? c) ? ja package power dissipation rating note) for the actual usage, please refer to the p d -ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. this value is based on the data lsi mount on pcb grass epoxy : 50 x 50 x 0.8 t ( mm ). caution note) this product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. this rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. when subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1: vb max = vbdcdc = vbled = vb, vled max = vled1 = vled2. the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for ta = 25 ? c. although this lsi has built-in esd protection circuit, it may st ill sustain permanent damage if not handled properly. therefore, proper esd precautions are recommended to avoid electrostatic damage to the mos gates. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 4 of 96 product standards recommended operating conditions *2 v vled + 0.3 ? ?0.3 bl1, bl2, bl3, bl4, bls1, bls2, pl1, pl2, r1, g1, b1, r2, g2, b2, ldo1, ldo2, lx, x0, x1, x2, x3, x4, x5, x6, y0, y1, y2, y3, y4, y5, y6 4.6 3.1 *1 v 3.7 vb *2 v vb + 0.3 ? ?0.3 ledcnt, ldocnt, fb ? ? 5.0 typ. ? v 3.0 ?0.3 ledctl, rstb, csb, clk, di, extclk, vibctl, gpi1, gpi2, gpi3, gpio1, gpio2 input voltage range ?0.3 3.1 min. *1 v 5.6 vled supply voltage range ? v 3.0 gpo1, gpo2, int, do output voltage range note unit max. symbol parameter note) *1: the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. do not apply external currents and voltages to any pin not specifically mentioned. voltage values, unless otherwise specified, are with respect to gnd. gnd is voltage for agnd, dgnd, ledgnd1, ledgnd2, rgbgnd1, rgbgnd2, dcdcgnd, pgnd1 and pgnd2. vb is voltage for vb dcdc, vbled and vb. vled is voltage for vled1 and vled2. *2: (vb + 0.3 ) v must not exceed 6 v. (vled + 0.3) v must not exceed 6.5 v. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 5 of 96 product standards ? ? a 1 ? ? ldocnt = high reg18 = low v ldo1 = 0 v, ioff1 = i ldo1 ioff1 leakage current when ldo1 turns off ? ? a 12 8 ? at standby mode ldocnt = low ldo2 is active. icc2 current consumption (2) ? v 1.91 1.85 1.79 i ldo1 = ? 30 ma vl1 output voltage ? ma 200 100 50 ldocnt = high reg18 = high v ldo1 = 0 v, ipt1 = i ldo1 ipt1 short circuit protection current ? db ?40 ?45 ? vb = 3.6 v + 0.2 v[p-p] f = 1 khz i ldo1 = ? 15 ma psl11 = 20log(acv ldo1 / 0.2) psl11 ripple rejection (1) ? db ?25 ?35 ? vb = 3.6 v + 0.2 v[p-p] f = 10 khz i ldo1 = ? 15 ma psl12 = 20log(acv ldo1 / 0.2) psl12 ripple rejection (2) v v 0.64 1.27 reference current ? 0.54 0.44 i iref = 0 ? a viref output voltage voltage regulator (ldo1) ? ? a 24 18 ? ldocnt = high ldo1 and ldo2 are active. icc3 current consumption (3) ? 1.24 1.21 i vref = 0 ? a vref output voltage reference voltage current consumption ? ? a 1 0 ? at off mode ldocnt = low icc1 current consumption (1) limits typ unit max note min condition symbol parameter electrical characteristics vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 6 of 96 product standards ? ms 30 13 3 time when int is set to high from low, after short detection. tscp short detection delay time *1 mhz 1.44 1.20 0.96 oscen = [1] , ddsw = [1] fdc oscillation frequency ? v 5.57 5.3 5.03 mode 2 iout = ? 400 ma vdc2 output voltage (2) ? v 5.16 4.89 4.62 mode 1 iout = ? 400 ma vdc1 output voltage (1) ? db ?30 ?35 ? vb = 3.6 v + 0.2 v[p-p] f = 1 khz i ldo2 = ? 15 ma psl21 = 20log(acv ldo2 / 0.2) psl21 ripple rejection (1) ? ma 300 100 50 ldocnt = high v ldo2 = 0v ipt2 = i ldo2 ipt2 short circuit protection current ? ? a 1 ? ? ldocnt = low reg28 = low v ldo2 = 0 v ioff2 = i ldo2 ioff2 leakage current when ldo2 turns off ? v 2.94 2.85 2.76 i ldo2 = ? 30 ma vl2 output voltage ? ? 4.8 2 ? i y0, y1, y2, y3, y4, y5, y6 = ? 5 ma rscan = v y0, y1, y2, y3, y4, y5, y6 / 5 ma rscan resistance at the switch on scan switch step-up dc/dc converter voltage regulator (ldo2) ? db ?15 ?25 ? vb = 3.6 v + 0.2 v[p-p] f = 10 khz i ldo2 = ? 15 ma psl22 = 20log(acv ldo2 / 0.2) psl22 ripple rejection (2) limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. *1: make sure to set both bits of oscen and ddsw to [1]. during oscen = [1] , ddsw must be set to [1]. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 7 of 96 product standards ? ? a 1 ? ? at current off setup v bl1, bl2, bl3, bl4 = 4.75 v iblsoff = i bl1, bl2, bl3, bl4 ibloff leakage current when bl1 ~ bl4 turn off *2 ma 8.957 8.294 7.630 at 8 ma setup v bl1, bl2, bl3, bl4 = 1 v ibls8 = i bl1, bl2, bl3, bl4 ibl8 output current (4) *2 ma 4.470 4.139 3.808 at 4 ma setup v bl1, bl2, bl3, bl4 = 1 v ibls4 = i bl1, bl2, bl3, bl4 ibl4 output current (3) *2 ma 2.223 2.058 1.894 at 2 ma setup v bl1, bl2, bl3, bl4 = 1 v ibls2 = i bl1, bl2, bl3, bl4 ibl2 output current (2) *2 ma 1.109 1.027 0.945 at 1ma setup v bl1, bl2, bl3, bl4 = 1 v ibls1 = i bl1, bl2, bl3, bl4 ibl1 output current (1) ? ? 5 ? ?5 at 15 ma setup the average value of all channels, and the current error of each channel iblch the error between channels current generator (for backlights) *2 ma 18.214 16.865 15.516 at 16 ma setup v bl1, bl2, bl3, bl4 = 1 v ibls16 = i bl1, bl2, bl3, bl4 ibl16 output current (5) limits typ unit max note min condition symbol parameter *2: values when recommended parts (erj2 rhd273x) are used for iref terminal. the other current settings are combination of above items. electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 8 of 96 product standards ? ? a 1 ? ? at current off setup v bls1, bls2 = 4.75 v iblsoff = i bls1, bls2 iblsoff leak current at the time of off *2 ma 9.011 8.344 7.677 at 8 ma setup v bls1, bls2 = 1 v ibls8 = i bls1, bls2 ibls8 output current (4) *2 ma 4.480 4.149 3.818 at 4 ma setup v bls1, bls2 = 1 v ibls4 = i bls1, bls2 ibls4 output current (3) *2 ma 2.244 2.078 1.912 at 2 ma setup v bls1, bls2 = 1 v ibls2 = i bls1, bls2 ibls2 output current (2) *2 ma 1.114 1.032 0.949 at 1ma setup v bls1, bls2 = 1 v ibls1 = i bls1, bls2 ibls1 output current (1) ? ? 5 ? ?5 at 15 ma setup the average value of all channels, and the current error of each channel iblsch the error between channels current genera tor (for sub backlights) *2 ma 17.998 16.665 15.331 at 16 ma setup v bls1, bls2 = 1 v ibls16 = i bls1, bls2 ibls16 output current (5) limits typ unit max note min condition symbol parameter *2: values when recommended parts (erj2 rhd273x) are used for iref terminal. the other current settings are combination of above items. electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 9 of 96 product standards *2 ma 17.861 16.538 15.215 at 16 ma setup v pl1, pl2 = 1 v ipl16 = i pl1, pl2 ipl16 output current (5) ? ? a 1 ? ? at current off setup v pl1, pl2 = 4.75 v iploff = i pl1, pl2 iploff leak current at the time of off *2 ma 8.835 8.180 7.526 at 8 ma setup v pl1, pl2 = 1 v ipl8 = i pl1, pl2 ipl8 output current (4) *2 ma 4.410 4.083 3.757 at 4 ma setup v pl1, pl2 = 1 v ipl4 = i pl1, pl2 ipl4 output current (3) *2 ma 2.215 2.051 1.887 at 2 ma setup v pl1, pl2 = 1 v ipl2 = i pl1, pl2 ipl2 output current (2) *2 ma 1.105 1.024 0.942 at 1ma setup v pl1, pl2 = 1 v ipl1 = i pl1, pl2 ipl1 output current (1) ? % 5 ? ?5 at 15 ma setup the average value of all channels, and the current error of each channel iplch the error between channels current generator (for photo flashes) *2 ma 33.156 30.700 28.244 at 30ma setup v pl1, pl2 = 1 v ipl30 = i pl1, pl2 ipl30 output current (6) limits typ unit max note min condition symbol parameter *2: values when recommended parts (erj2 rhd273x) are used for iref terminal. the other current settings are combination of above items. electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 10 of 96 product standards *2 ma 16.693 15.456 14.220 at 15 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx15 = i x0, x1, x2, x3 , x4, x5, x6 imx15 output current (5) ? ? 5 ? ?5 the average value of all channels, and the current error of each channel imxch the error between channels *2 ma 8.781 8.131 7.480 at 8 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx8 = i x0, x1, x2, x3, x4, x5, x6 imx8 output current (4) *2 ma 4.393 4.068 3.742 at 4 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx4 = i x0, x1, x2, x3, x4, x5, x6 imx4 output current (3) *2 ma 2.181 2.019 1.858 at 2 ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx2 = i x0, x1, x2, x3, x4, x5, x6 imx2 output current (2) *2 ma 1.080 1.000 0.920 at 1ma setup v x0, x1, x2, x3, x4, x5, x6 = 1 v imx1 = i x0, x1, x2, x3, x4, x5, x6 imx1 output current (1) current generator (for 7*7 dots matrix led) ? ? a 1 ? ? current off setup v x0, x1, x2, x3, x4, x5, x6 = 4.75 v imxoff = i x0, x1, x2, x3 , x4, x5, x6 imxoff leak current at the time of off limits typ unit max note min condition symbol parameter *2: values when recommended parts (erj2 rhd273x) are used for iref terminal. the other current settings are combination of above items. electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 11 of 96 product standards switch of pch-mos (vled1) ? ? 20 5 ? vbled = 2.2 v v chggnd = 0 v i led1 = ? 10 ma rvled = ( 2.2 v ? v led1 ) / 10 ma rvled vbled ? vled output impedance switch of nch-mos (r1, r2, g2, b2) ? ? 50 10 ? vb = 2.2 v v chggnd = 0 v i r1 = 5 ma rr1 = v r1 / 5 ma rr1 r1 output impedance ? ? 30 10 ? register : 19hd4 = high i r2 = 5 ma rr2 = v r2 / 5 ma rr2 r2 output impedance ? ? 30 10 ? register : 19hd3 = high i g2 = 5 ma rg2 = v g2 / 5 ma rg2 g2 output impedance ? ? a 1 ? ? current off setup v r1, g1, b1, r2, g2, b2 = 4.75 v irgboff = i r1, g1, b1, r2, g2, b2 irgboff leak current at the time of off ? ? 30 10 ? register : 19hd2 = high i b2 = 5 ma rb2 = v b2 / 5 ma rb2 b2 output impedance *2 ma 8.881 8.223 7.566 at 8 ma setup v r1, g1, b1 = 1 v irgb8 output current (4) *2 ma 4.434 4.105 3.777 at 4 ma setup v r1, g1, b1 = 1 v irgb4 output current (3) *2 ma 2.234 2.068 1.903 at 2 ma setup v r1, g1, b1 = 1 v irgb2 output current (2) *2 ma 1.115 1.032 0.950 at 1ma setup v r1, g1, b1 = 1 v irgb1 output current (1) current generator (for rgb color unit) ? % 5 ? ?5 the average value of all channels, and the current error of each channel irgbch the error between channels limits typ unit max note min condition symbol parameter *2: values when recommended parts (erj2 rhd273x) are used for iref terminal. the other current settings are combination of above items. electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 12 of 96 product standards ? v ldo1 + 0.3 ? 1.4 high-level recognition voltage (ldo1 mode) vih1 input voltage range of high- level 1 ? v ldo2 + 0.3 ? 2.1 high-level recognition voltage (ldo2 mode) vih2 input voltage range of high- level 1 ? v 0.4 ? ?0.3 low-level recognition voltage vil input voltage range of low- level ? ? a 1 0 ? v gpi1, gpi2, gpi3, gpio1, gpio2 = 2.85 v iih = i gpi1, gpi2, gpi3, gpio1, gpio2 iih input current of high-level ? ? a 1 0 ? v gpi1, gpi2, gpi3, gpio1, gpio2 = 0 v iil = i gpi1, gpi2, gpi3, gpio1, gpio2 iil input current of low-level gpio i/f, gpi i/f gpio i/f, gpo i/f, int ? v ? ? ldo2 ? 0.8 i gpo1, gpo2, gpio1, gpio2, int = ? 2 ma vddsel = ldo2 voh1 output voltage of high-level (1) ? v ldo2 ? 0.2 (0.15) ? ? i gpo1, gpo2, gpio1, gpio2, int = 2 ma vddsel = ldo2 (i gpo1, gpo2, gpio1, gpio2, int = 0.5 ma ) vol1 output voltage of low-level (1) ? v ? ? ldo1 ? 0.8 i gpo1, gpo2, gpio1, gpio2, int = ? 2 ma vddsel = ldo1 vol2 output voltage of high-level (2) ? v ldo1 ? 0.3 (0.15) ? ? i gpo1, gpo2, gpio1, gpio2, int = 2 ma vddsel = ldo1 (i gpo1, gpo2, gpio1, gpio2, int = 0.5 ma ) vol2 output voltage of low-level (2) ? ? a 1 0 ? v ledctl, rstb, csb, clk, di = 0 v iil = i ledctl, rstb, csb, clk, di iil input current of low-level ? ? a 1 0 ? v ledctl, rstb, csb, clk, di = 1.85 v iih = i ledctl, rstb, csb, clk, di iih input current of high-level ? v 0.4 ? ?0.3 low-level recognition voltage vil input voltage range of low- level ? v ldo1 + 0.3 ? 1.4 high-level recognition voltage vih input voltage range of high- level spi i/f, ledctl, rstb limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 13 of 96 product standards ? ? 130k 100k 70k i test1, test2, gpi1, gpi2, gpi3 = 5 ? a rpd = v test1, test2, gpi1, gpi2, gpi3 / 5 ? a rpd pull-down resistance test1, test2, gpi1, gpi2, gpi3 ? v 3.3 ? 2.1 high-level recognition voltage vih input voltage range of high- level ? v 0.4 ? ?0.3 low-level recognition voltage vil input voltage range of low- level ? v 1 0 ? v vibctl = 3.0 v iih = i vibctl iih input current of high-level ? ? a 1 0 ? v vibctl = 0 v iil = i vibctl iil input current of low-level vibctl do ? v ? ? ldo1 ? 0.8 i do = ? 2 ma voh3 output voltage of high-level ? v ldo1 ? 0.2 ? ? i do = 2 ma vol3 output voltage of low-level gpio1, gpio2 ? ? 130k 100k 70k i gpio1, gpio2 = 0 ? a rpu1 = v gpio1, gpio2 i gpio1, gpio2 = ? 5 ? a rpu = ( rpu1 ? v gpio1, gpio2 ) / 5 ? a rpu pull-up resistance ? ? a 1 0 ? v ldocnt, ledcnt = 0 v iil = i ldocnt, ledcnt iil input current of low-level ? ? a 1 0 ? v ldocnt, ledcnt = 3.6 v iih = i ldocnt, ledcnt iih input current of high-level ? v 0.4 ? ?0.3 low-level recognition voltage vil input voltage range of low- level ? v vb + 0.3 ? vb ? 0.7 high-level recognition voltage vih input voltage range of high- level ldocnt, ledcnt limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 14 of 96 product standards ? ma 3.0 1.2 ? current when dc/dc converter is active. idc1 dc/dc control current (1) ? ma 1.4 0.7 ? current when dc/dc converter is inactive and the automatic control circuit is operating idc2 dc/dc control current (2) current consumption of dc/dc converter part ? v 0.44 0.40 0.36 voltage which dc/dc converter turns on when the voltage of bl1, bl2, bl3, bl4, bls1, and bls2 terminal falls vmon detection voltage dc/dc converter automatic control part limits typ unit max note min condition symbol parameter electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 15 of 96 product standards max typ note unit limits condition symbol parameter min ? ? ? i ldo1 = ? 15 ma ? ? 50 ? a(1 ? s) i ldo1 = ? 50 ? a ? ? 15 ma (1 ? s) time until output voltage reaches to 10 % time until output voltage reaches to 0 v to 90 % *3 *4 ? s ? 250 ? time until output voltage reaches to 0 v to 90 % tsu2 rise time *3 *4 ms ? 5 ? time until output voltage reaches to 10 % tsd2 fall time *4 mv ? 70 ? i ldo2 = ? 50 ? a ? ? 15 ma (1 ? s) vtr21 load transient response (1) *4 mv ? 70 ? i ldo2 = ? 15 ma ? ? 50 ? a(1 ? s) vtr22 load transient response (2) *4 ? f ? 1.0 ? ? cldo2 output capacity range *3 *4 ? s ? 250 ? tsu1 rise time *3 *4 ms ? 5 ? tsd1 fall time *4 mv ? 70 ? vtr11 load transient response (1) *4 mv ? 70 ? vtr12 load transient response (2) *4 ? f ? 1.0 ? cldo1 output capacity range *4 ? ? 0.05 ? resr1 output capacity esr tolerance level *5 ma ? 15 ? imax1 maximum output current *4 ? ? 0.05 ? ? resr2 output capacity esr tolerance level *5 ma ? 15 ? ? imax2 maximum output current voltage regulator (ldo2) voltage regulator (ldo1) *5 : this ic consumes each 5ma maximum from ldo1 and ldo2 for the internal circuit. when it is used to supply external components, it must be used within 25ma load current. note) *3 : rise time and fall time are defined as below. *4 : typical design value ldocnt serial ldo2 10% 90% tsu2 tsd2 ldo1 90% 10% tsu1 tsd1 electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 16 of 96 product standards max typ note unit limits condition symbol parameter min *4 ? f ? 22 ? ? cdc1 output capacity range *4 v ? 1 ? i dcdcout = ? 400 ma ? ? 50 ? a(1 ? s) vtrdc2 load transient response (2) time after the voltage of bl1 to 4 / bls1 to 2 goes under 0.4 v until it detects coincidence 3 times and dc/dc converter operates. time after excess voltage is detected until int is set to high from low vled voltage which detects excess voltage ? i dcdcout = ? 50 ? a ? ? 400 ma (1 ? s) time until output voltage reaches to 3.8 v from 4.9 v i dcdcout = 0 ma time until output voltage reaches to 90 % from battery voltage *4 *7 ? c ? 160 ? temperature which ldo1, ldo2, dc/dc, constant current circuit, matrix sw and rgb turns off. tdet detection temperature *4 *8 ? c ? 110 ? returning temperature tsd11 return temperature *4 *6 ms ? 1 ? tsu11 rise time *4 *6 s ? 1 ? tsd11 fall time *4 v ? 1 ? vtrdc1 load transient response (1) *4 ? ? 0.30 ? resr1 output capacity esr tolerance level *4 v ? 6.2 ? vovp excess voltage detection voltage *4 ms ? 12.75 ? tovp delay time of excess voltage detection voltage *4 ms ? 2.0 ? tmon delay time of constant voltage circuit monitor tsd (thermal shutdown circuit) step-up dc/dc converter electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *4 : typical design value *6, *7, *8 : refer to the next page d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 17 of 96 product standards note) *6 : *7: ldo1, ldo2, dc/dc converter, constant current circuit, and matrix sw and rgb are turned off when tsd is high. when tsd is high, the register is set as 14hd 1 = 1. however, data can be read only when the register is read immediately after int occurs since internal regulator is turned off. *8: only ldo1 and ldo2 return after on state of tsd. a logic part will be in reset state. lx fb serial 4.7 ? h 22 ? f vled1 vled2 dcdcgnd dcdcout vbatt 0.3 ? vbdcdc 10 ? f vlf4012at-4r7m1r1-7 cph5811 ceramics psla21a106m x 2 pslb31a226m dcdc serial dcdcout 90% 10% rise time fall time electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 18 of 96 product standards max typ note unit limits condition symbol parameter min *4 ns ? 60 ? ? twlc1 clk cycle time low period *4 ns ? 25 ? only read tdodly1 dc delay time *4 ns ? 5 ? ? tcgh1 chip enable hold time *4 ns ? 62 ? ? tsh1 serial-data hold time *4 ns ? 62 ? ? tcsw1 transceiver interval *4 ns ? 5 ? ? tcss1 chip enable setup time *4 ns ? 62 ? ? tss1 serial-data setup time microcomputer interface characteristic (vdd = 1.85 v ? 3%) *4 ns ? 125 ? ? tscyc1 clk cycle time *4 ns ? 60 ? ? twhc1 clk cycle time high period microcomputer interface timing chart twlc1 clk do di tscyc1 tsh1 tss1 csb tcss1 tcsw1 tcgh1 tdodly1 twhc1 electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *4 : typical design value d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 19 of 96 product standards max typ note unit limits condition symbol parameter min *4 ns ? 62 ? ? tcsw2 transceiver interval *4 ns ? 60 ? ? twlc2 blsclk cycle time low period *4 ns ? 62 ? ? tsh2 serial-data hold time *4 ns ? 5 ? ? tcss2 blsce setup time *4 ns ? 5 ? ? tcgh2 blsce hold time ? *4 ns ? 62 ? ? tss2 serial-data setup time spi2 format microcomputer interface characteristic (vdd = 1.85 v ? 3%) *4 ns ? 125 ? ? tscyc2 blsclk cycle time *4 ns ? 60 ? twhc2 blsclk cycle time high period blsdat operation gpi3 operation gpi3 terminal spi2 operation blsclk operation blsce operation 1 gpio operation gpi2 operation gpi1 operation 0 operation gpi2 terminal gpi1 terminal sersel blsclk blsdat blsce spi1 spi2 reg 05h constant current circuit lcdmain sersel tcgh2 tcss2 tcsw2 d7 tsh2 tscyc2 tss2 d6 d5 d4 d3 d2 d1 d0 twhc2 twlc2 electrical characteristics (continued) vb = vbdcdc = vbled = 3.6 v, vled1 = vled2 = 4.9 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *4 : typical design value d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 20 of 96 product standards pin configuration top view 1 2 3 4 5 6 7 8 9 j h g f e d c b a y0 vled1 r1 r2 x6 y1 x5 pgnd 2 x4 x3 test 1 x2 pgnd 1 y2 y3 vled2 vb led y4 di ext clk x1 x0 gpo 2 int gpo 1 pl2 bl4 bl2 bl1 rgb gnd2 y5 rstb y6 test 2 csb do vib ctl led ctl led cnt iref ldo1 ldo cnt lx vrefd agnd ldo2 vb fb vb dcdc pl1 led gnd2 bl3 led gnd1 bls2 bls1 chg gnd b2 b1 g2 gpi 1 clk gpio 1 gpio 2 gpi 2 gpi 3 g1 rgb gnd1 dcdc gnd dgnd d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 21 of 96 product standards pin functions constant current circuit. the output terminal of pwm control. it connects with the 1st row of matrix led. output x0 g1(1) constant current circuit. the output terminal of pwm control. it connects with the 2nd row of matrix led. output x1 g2(2) constant current circuit. the output terminal of pwm control. it connects with the 3rd row of matrix led. output x2 f2(3) constant current circuit. the output terminal of pwm control. it connects with the 4th row of matrix led. output x3 e1(4) the gnd terminal for matrix led ground pgnd1 pgnd2 f1(5) d1(6) constant current circuit. the output terminal of pwm control. it connects with the 5th row of matrix led. output x4 e2(7) constant current circuit. the output terminal of pwm control. it connects with the 6th row of matrix led. output x5 d2(8) constant current circuit. the output terminal of pwm control. it connects with the 7th row of matrix led. output x6 c1(9) constant current circuit. the output terminal of pwm control. it connects with the a column of matrix led. output y0 a3(10) constant current circuit. the output terminal of pwm control. it connects with the b column of matrix led. output y1 b4(11) constant current circuit. the output terminal of pwm control. it connects with the c column of matrix led. output y2 a5(12) constant current circuit. the output terminal of pwm control. it connects with the d column of matrix led. output y3 b5(13) the power supply's connect terminal for matrix led. connect with the output of battery or step-up dc/dc converter. power supply vled1 vled2 a4(14) a6(15) constant current circuit. the output terminal of pwm control. it connects with the e column of matrix led. output y4 b6(16) constant current circuit. the output terminal of pwm control. it connects with the f column of matrix led. output y5 a7(17) constant current circuit. the output terminal of pwm control. it connects with the g column of matrix led. output y6 b7(18) description type pin name pin no. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 22 of 96 product standards pin functions (continued) the feedback terminal for step-up dc/dc converter. input fb f9(19) the gnd terminal for step-up dc/dc converter. ground dcdcgnd h9(20) the terminal for external nch-type mos-tr gate driver. output lx g8(21) the power supply's connect terminal for step-up dc/dc converter. power supply vbdcdc g9(22) led contact terminal. control by ledcnt terminal is also possible. output r1 b3(23) led contact terminal. output g1 c5(24) led contact terminal. output b1 c4(25) the gnd terminal for rgb terminal. ground rgbgnd1 rgbgnd2 a2(26) b1(27) general-purpose output terminal.(nch-mos open drain) output r2 c2(28) general-purpose output terminal.(nch-mos open drain) output g2 c3(29) general-purpose output terminal.(nch-mos open drain) output b2 d3(30) the resistance contact terminal for charge led.(connect current restriction resistance between this terminal and gnd terminal.) output chggnd d4(31) battery voltage's connect terminal. this terminal supplies power supply to r1 terminal and r2 terminal. power supply vbled c6(32) on/off control terminal of led connected to r1 terminal and r2 terminal. input ledcnt c8(33) ldo2 (2.85 v) output terminal. output ldo2 d9(34) the power supply's connect terminal for bgr circuit and ldo circuit. power supply vb e9(35) ldo1 (1.85 v) output terminal. output ldo1 e8(36) on/off control terminal of ldo1 and ldo2. input ldocnt f8(37) bgr circuit output terminal. output vrefd c9(38) the resistance connect terminal for constant current value setup. output iref d8(39) description type pin name pin no. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 23 of 96 product standards pin functions (continued) the constant current output terminal for led driver. (0 to 61 ma) this terminal is driven with the same current value as pl2 terminal. output pl1 j3(40) the constant current output terminal for led driver. (0 to 61 ma) this terminal is driven with the same current value as pl1 terminal. output pl2 h3(41) the gnd terminal for constant current circuits for led driver. ground ledgnd1 ledgnd2 j5(42) j2(43) the constant current output terminal for led driver. (0 to 31 ma) this terminal is driven with the same current value as bl2, bl3 and bl4 terminal. output bl1 h6(44) the constant current output terminal for led driver. (0 to 31 ma) this terminal is driven with the same current value as bl1, bl3 and bl4 terminal. output bl2 h5(45) the constant current output terminal for led driver. (0 to 31 ma) this terminal is driven with the same current value as bl1, bl2 and bl4 terminal. output bl3 j4(46) the constant current output terminal for led driver. (0 to 31 ma) this terminal is driven with the same current value as bl1, bl2 and bl3 terminal. output bl4 h4(47) the constant current output terminal for led driver. (0 to 31 ma) this terminal is driven with the same current value as bls2 terminal. output bls1 j7(48) the constant current output terminal for led driver. (0 to 31 ma) this terminal is driven with the same current value as bls1 terminal. output bls2 j6(49) the gnd terminal for analog circuitry. ground agnd b9(50) interrupt output terminal. output int g5(51) test terminal. input test1 f3(52) test terminal. input test2 d7(53) chip-enable terminal for spi1 interface. input csb e7(54) clock input terminal for spi1 interface. input clk e6(55) data input terminal for spi1 interface. input di f6(56) data output terminal for spi1 interface. output do f7(57) reset input terminal input rstb c7(58) description type pin name pin no. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 24 of 96 product standards external clock input terminal. (it can operate by the clock frequency of a maximum of 1.44 mhz.) input extclk g3(59) the gnd terminal for logic circuitry. ground dgnd j8(60) gpi input port terminal. (chip-enable terminal for spi2 interface.) input gpi1 e3(61) gpi input port terminal. (clock input terminal for spi2 interface.) input gpi2 f5(62) gpi input port terminal. (data input terminal for spi2 interface.) input gpi3 f4(63) gpo output port terminal. output gpo1 g6(64) gpo output port terminal. output gpo2 g4(65) gpio input/output port terminal. input / output gpio1 d6(66) gpio input/output port terminal. input / output gpio2 d5(67) led's lighting on/off control terminal. (it is based on register 0ah.) input ledctl h7(68) led's lighting on/off control terminal. (it is based on register 09h.) input vibctl g7(69) description type pin name pin no. pin functions (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 25 of 96 product standards functional block diagram x0 lx vb agnd bls2 bls1 bl4 bl3 bl2 bl1 x1 x2 x3 x4 x5 x6 y0 y1 y2 y3 y4 y5 y6 pl2 vrefd pl1 ldo2 ldo1 ldocnt int dgnd vibctl gpi1 gpi2 gpi3 gpo1 gpo2 gpio2 gpio1 di do ext clk rstb led gnd2 vbdcdc pgnd2 ledcnt vbled csb clk test2 test1 ledctl vled1 vled2 b2 g2 r2 r1 g1 b1 pgnd1 dcdcgnd fb rgbgnd2 ledgnd1 iref rgbgnd1 chggnd bgr tsd step-up dc/dc converter e1(4) g1(1) g2(2) f2(3) e2(7) d2(8) c1(9) a5(12) a3(10) b4(11) b5(13) b6(16) a7(17) b7(18) constant current control (7-ch) pwm control (7-ch) scan switch (7-ch) g6(64) f4(63) f5(62) e3(61) e9(35) d9(34) e8(36) f8(37) c9(38) h6(44) h5(45) j4(46) h4(47) j7(48) j6(49) back light constant current control (6-ch) photo flash constant current control (2-ch) j8(60) g7(69) ldo2 2.85 v/30ma ldo1 1.85 v/30ma gpio d5(67) d6(66) g4(65) spi2 register pattern register ram fixed pattern rom command decoding blsdat blsclk blsce dac (2-ch) dac (6-ch) c8(33) spi1 g8(21) iref g9(22) h7(68) a4(14) a6(15) d3(30) c3(29) c2(28) b3(23) c5(24) c4(25) rgb control f1(5) d1(6) h9(20) f9(19) b1(27) c6(32) j3(40) h3(41) j5(42) d8(39) j2(43) b9(50) g5(51) f3(52) d7(53) e7(54) e6(55) f6(56) f7(57) c7(58) g3(59) level shift level shift on/off standby on/off htsd on/off a2(26) d4(31) on/off notes: this block diagram is for explaining functions. part of the block diagram may be omitted, or it may be simplified. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 26 of 96 product standards ? 18 n.c. (on) n.c. (on) low ? high high : on at standby mode low : off high : on < 1 (off mode ) or 8 (standby mode) 18 < 1 itotal typ ( ? a) low : off at off mode n.c. (on) off reg28 ? regardless of the value of reg18, ldo1 turns on at ldocnt = high. ? regardless of the value of reg28, ldo2 turns on at ldocnt = high. ? serial interface signal is not received at rstb = low ? 5 ms after being set to ldocnt = high, the receptionist of serial interface signal is attained. ? to activate rstb, rstb should be kept low for more than one internal clock period. ? rstb terminal prohibits the input signal of those other than a rectangle wave. n.c. (off) high ? low ? the signal from serial interface is not received in ldocnt = low and the state of reg28 = low or reg18 = low. ? it shifts to standby mode with ldocnt = low and reg28 = high. ? the signal from serial interface is not received at standby-mode. (power supply for logic is ldo1 and ldo2.) therefore, standby release by the signal from serial interface cannot be performed. ? in standby-mode, if ldocnt is switched to high from low, it will return to the normal mode. ? it cannot shift to off-mode from standby- mode. once returning to the normal mode, please shift to off-mode. ? rstb = low is prohibited in standby-mode. (an internal circuit becomes unfixed.) ? do not impress voltage to gpi1, gpi2, gpi3, gpio1, and gpio2 terminal in standby-mode. n.c. (on) high ? it is necessary to make it ldocnt = high for the return from off-mode. ? rstb = low is forb idden at o ff-mode. (an internal circuit becomes unfixed.) ? do not impress voltage to gpi1, gpi2, gpi3, gpio1, and gpio2 te rminal at off-mode. off low (initial condition) notes reg18 ldocnt operation 1. explanation of each mode ( power supply startup sequence ) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 27 of 96 product standards * this is the waveform in the case of applying reset to register setup at standby mode. * maintain the state of rstb = high to hold the register setup. ldocnt ldo1 ldo2 reg18 reg28 a register input is possible. over 5 ms ldocnt ldo1 ldo2 reg18 reg28 a register input is possible. ? shift to the normal mode from standby mode rstb over 3 ms rstb over 5 ms over 3 ms low power mode ? shift to the norma l mode from off-mode operation (continued) 1. explanation of each mode ( power supply startup sequence ) (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 28 of 96 product standards ? shift to the standby mode from normal mode ldocnt ldo1 ldo2 reg18 reg28 over 1 ms a register input is possible. set reg18 to low before ldocnt. low power mode rstb ldocnt ldo1 ldo2 reg18 reg28 over 1 ms set reg18 and reg28 to low before ldocnt. a register input is possible. rstb over 3 ms ? shift to the off-mode from normal mode operation (continued) 1. explanation of each mode ( power supply startup sequence ) (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 29 of 96 product standards y0 y1 y2 y3 y5 x0 to x6 y4 y6 6671clk (about 180.83 hz) 8clk (6.67 ? s) 945clk (787.5 ? s) minimum width of pwm 63clk (52.5 ? s) the following waveform is an internal signal. in following yx = xx = low, the waveform of actual yx terminal is set to hi-z. matrix part operation waveform operation (continued) 2. explanation of operation d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 30 of 96 product standards v dcdc output 6.2 v v ldo2 0 v v serial ddsw ldo2 0 v 0 v v lx vb 0 v 4.9 v fb terminal is open latch release will be carried out if serial ddsw is set to low. fb the shut after about 13 ms after dc/dc output voltage is set to about 6.2 v. vb time time time time about 8 ms about 13 ms internal shutdown signal explanation of excess voltage protection circuit of operation operation (continued) 2. explanation of operation (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 31 of 96 product standards v 0 v ldo2 0 v ldo2 0 v 0 v lx vb 0 v 4.9v vb time time time time time v v v v fb a shutdown is generated, w hen the output voltage of internal error amplifier goes up, and duty max state is set to about 13 ms or more. latch release will be carried out if serial ddsw is set to low. serial ddsw dc/dc output is short-circuited to gnd. dcdc output about 8 ms internal error amplifier output voltage internal shutdown signal about 13 ms explanation of over-current protection circuit of operation operation (continued) 2. explanation of operation (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 32 of 96 product standards reg28 bgr vbatt tsd ldocnt vb ce clk di do level shift register rst rstb ldo2 2.85 v 1 ? f 1 ? f ldo2 ldo1 ldo1 1.85 v reg18 all the logic portions to which the power supply is not connected are connected to vb as power supplies. level shift on/off on/off standby on/off htsd on/off 1 ? f vrefd level shift ldo1 ldo2 ldo1 ldo2 ldo2 vb ldo2 reset part block configuration operation (continued) 3. block configuration d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 33 of 96 product standards all the logic portions to which the power supply is not connected are connected to vb as power supplies. adjust r value with the led and current you use. vbatt vbled 22 ? f vled1 lx dc/dc ledcnt[vb] 4.7 ? h r1 *r 100 k ? 0.3 ? this function cannot be used when dc/dc converter is active. vled2 fb ddsw gndchg dgnd vlf4012 cph5811 the led part for charge block configuration operation (continued) 3. block configuration (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 34 of 96 product standards a b c d efg 1 2 3 4 5 6 7 y0 y1 y2 y3 y4 y5 y6 x0 x1 x2 x3 x4 x5 x6 the connected terminal name led?s number led?s number explanation of matrix led part, matrix led?s number operation (continued) 3. block configuration (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 35 of 96 product standards ? ? tsd cpuw rer frmin t rama ct ? ? err2 eh facg d1 iofac tor r 14h ? disrg b1 dismt x dissu b2 dissu b1 displ 2 displ 1 leda ct ledct l w 0ah w/r w/r w/r w/r w/r r w/r w/r w/r w/r w w w w w r w w w r/w iovse l2 ovsel2 ? iosta2 iosta1 ista3 ista2 ioout 2 ioout 1 oout2 oout1 imsk2 iomsk 1 imsk3 imsk2 pwmc lk bls2m bls1m bl4m bl3m bl2m bl1m ? pwmc nt 08h iodet[1:0] idet[1:0] ? ? ? ? iodet 18h iochat2[1:0] iochat1[1:0] ? ? ? ? iocha t 17h ichat3[1:0] ichat2[1:0] ichat1[1:0] ? ? ichat 16h ista1 ? ? stag d iosta te 15h iovse l1 ovsel 1 ? ? intvs el vdds el 1ah ioplu d2 ioplu d1 b2on g2on r2on ? ? ? ioplu d 19h gpioc lk ? ? ? ? ? ? ? gpioc nt 10h ? vibrg b1 vibmt x vibsu b2 vibsu b1 vibpl 2 vibpl 1 viba ct vibct l 09h plcnt[4:0] hien ? ? plcnt 07h lcdsub[4:0] ? ? ? lcdsu b 06h lcdmain[4:0] ? ? ? lcdm ain 05h lsiver[7:0] lsive r 04h serse l ? ? ? ? ? ? ? sers el 03h data name sub address ? ? ? ? ioout 13h imsk1 ? ? ? iomsk 12h iosel2 iosel1 ? ? ? ? ? ? iosel 11h reg28 reg18 ? ? ? ? ? ? ldoc nt 02h ddsw dcose l oscen vfoff ? ? powe rcnt 01h d5 d6 d7 data d0 d1 d2 d3 d4 operation (continued) 4. register and address register map d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 36 of 96 product standards ? ? ? ? ? ? ? ? ? ? ? prot 2 ? ? prot1 ? ? ? ? ? ? ? prot1 r/w 6bh ? prot2 r/w 6dh prot 3 prot3 r/w 6fh iofac2 iofa c1 ifac3 ifac2 ifac1 ovp scp facg d2 error r 2eh ramnum ? rgbon ? ? ? ? ? ? ? rgbon r/w 2ch rgbdata[5:0] ? ? rgbdata r/w 2dh scltime[1:0] ? ? ? ? ? ? ? scltime r/w 2bh settime[1:0] ? ? ? ? ? ? settime r/w 28h repon ? ? ? ? setto[7:0] setto r/w 26h sclon ? ? ? ? ? ? scroll r/w 2ah test6 test6 r/w 75h test1 test1 r/w 70h test2 test2 r/w 71h test3 test3 r/w 72h test4 test4 r/w 73h test5 test5 r/w 74h test6 test7 r/w 76h ram2 ram1 ? ? ? ? ? ? ramrst r/w 29h ? ? ? ? ? ? ramnum r/w 30h r/w r/w r/w r/w r/w r/w r/w r/w r/w test7 test8 77h ? ? ? ? ? ? setfrom[7:0] setfrom 25h ? ? repon 27h copysta rt selr am ? ? ramcopy 24h selrom[7:0] romsel 23h rom77[1:0] ? ? ? ? ? ffrom 22h data name sub address mtxdata[7:0] mtxdata 21h mtxon ? ? ? ? ? ? ? mtxon 20h d5 d6 d7 data d0 d1 d2 d3 d4 register map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 37 of 96 product standards dla1[1:0] fra1[1:0] bla1[3:0] a1 31h dla2[1:0] fra2[1:0] bla2[3:0] a2 32h dla3[1:0] fra3[1:0] bla3[3:0] a3 33h dla4[1:0] fra4[1:0] bla4[3:0] a4 34h dla5[1:0] fra5[1:0] bla5[3:0] a5 35h dla6[1:0] fra6[1:0] bla6[3:0] a6 36h dla7[1:0] fra7[1:0] bla7[3:0] a7 37h dlb1[1:0] frb1[1:0] blb1[3:0] b1 38h dlb2[1:0] frb2[1:0] blb2[3:0] b2 39h dlb3[1:0] frb3[1:0] blb3[3:0] b3 3ah dlb4[1:0] frb4[1:0] blb4[3:0] b4 3bh dlb5[1:0] frb5[1:0] blb5[3:0] b5 3ch dlb6[1:0] frb6[1:0] blb6[3:0] b6 3dh dlb7[1:0] frb7[1:0] blb7[3:0] b7 3eh dlc1[1:0] frc1[1:0] blc1[3:0] c1 3fh dlc2[1:0] frc2[1:0] blc2[3:0] c2 40h dlc3[1:0] frc3[1:0] blc3[3:0] c3 41h dlc4[1:0] frc4[1:0] blc4[3:0] c4 42h dlc5[1:0] frc5[1:0] blc5[3:0] c5 43h dlc6[1:0] frc6[1:0] blc6[3:0] c6 44h dlc7[1:0] frc7[1:0] blc7[3:0] c7 45h dld1[1:0] frd1[1:0] bld1[3:0] d1 46h dld2[1:0] frd2[1:0] bld2[3:0] d2 47h dld3[1:0] frd3[1:0] bld3[3:0] d3 48h dld4[1:0] frd4[1:0] bld4[3:0] d4 49h dld5[1:0] frd5[1:0] bld5[3:0] d5 4ah dld6[1:0] frd6[1:0] bld6[3:0] d6 4bh dld7[1:0] frd7[1:0] bld7[3:0] d7 4ch data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 ram address map operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 38 of 96 product standards dlg7[1:0] frg7[1:0] blg7[3:0] g7 61h dlledb1[1:0] dlledg1[1:0] dlledr1[1:0] frledb1[1:0] frledg1[1:0] frledr1[1:0] blledr1[3:0] ledr1 62h blledg1[3:0] ledg1 63h blledb1[3:0] ledb1 64h dle1[1:0] fre1[1:0] ble1[3:0] e1 4dh dle2[1:0] fre2[1:0] ble2[3:0] e2 4eh dle3[1:0] fre3[1:0] ble3[3:0] e3 4fh dle4[1:0] fre4[1:0] ble4[3:0] e4 50h dle5[1:0] fre5[1:0] ble5[3:0] e5 51h dle6[1:0] fre6[1:0] ble6[3:0] e6 52h dle7[1:0] fre7[1:0] ble7[3:0] e7 53h dlf1[1:0] frf1[1:0] blf1[3:0] f1 54h dlf2[1:0] frf2[1:0] blf2[3:0] f2 55h dlf3[1:0] frf3[1:0] blf3[3:0] f3 56h dlf4[1:0] frf4[1:0] blf4[3:0] f4 57h dlf5[1:0] frf5[1:0] blf5[3:0] f5 58h dlf6[1:0] frf6[1:0] blf6[3:0] f6 59h dlf7[1:0] frf7[1:0] blf7[3:0] f7 5ah dlg1[1:0] frg1[1:0] blg1[3:0] g1 5bh dlg2[1:0] frg2[1:0] blg2[3:0] g2 5ch dlg3[1:0] frg3[1:0] blg3[3:0] g3 5dh dlg4[1:0] frg4[1:0] blg4[3:0] g4 5eh dlg5[1:0] frg5[1:0] blg5[3:0] g5 5fh dlg6[1:0] frg6[1:0] blg6[3:0] g6 60h data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 ram address map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 39 of 96 product standards t alphabetic character 30 s alphabetic character 29 nothing all putting out lights 0 display contents of the pattern pattern no. r alphabetic character 28 q alphabetic character 27 p alphabetic character 26 o alphabetic character 25 n alphabetic character 24 m alphabetic character 23 l alphabetic character 22 k alphabetic character 21 j alphabetic character 20 i alphabetic character 19 h alphabetic character 18 g alphabetic character 17 f alphabetic character 16 e alphabetic character 15 d alphabetic character 14 c alphabetic character 13 b alphabetic character 12 a alphabetic character 11 9 number 10 8 number 9 7 number 8 6 number 7 5 number 6 4 number 5 3 number 4 2 number 3 1 number 2 0 number 1 w alphabetic character 59 x alphabetic character 60 y alphabetic character 61 display contents of the pattern pattern no. v alphabetic character 58 u alphabetic character 57 t alphabetic character 56 s alphabetic character 55 r alphabetic character 54 q alphabetic character 53 p alphabetic character 52 o alphabetic character 51 n alphabetic character 50 m alphabetic character 49 l alphabetic character 48 k alphabetic character 47 j alphabetic character 46 i alphabetic character 45 h alphabetic character 44 g alphabetic character 43 f alphabetic character 42 e alphabetic character 41 d alphabetic character 40 c alphabetic character 39 b alphabetic character 38 a alphabetic character 37 z alphabetic character 36 y alphabetic character 35 x alphabetic character 34 w alphabetic character 33 v alphabetic character 32 u alphabetic character 31 [00000000] - [10010101] : rom(only luminosity) 7 ? 7 pattern no.0 (default) to pattern no.149 rom address map operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 40 of 96 product standards katakana 92 katakana 91 z alphabetic character 62 display contents of the pattern pattern no. katakana 90 katakana 89 katakana 88 katakana 87 katakana 86 katakana 85 katakana 84 katakana 83 katakana 82 katakana 81 katakana 80 katakana 79 katakana 78 katakana 77 katakana 76 katakana 75 katakana 74 katakana 73 katakana 72 katakana 71 katakana 70 katakana 69 katakana 68 katakana 67 katakana 66 katakana 65 katakana 64 katakana 63 heart symbol 121 mail symbol 122 telephone symbol 123 display contents of the pattern pattern no. ` symbol 120 b symbol 119 a symbol 118 katakana 117 katakana 116 katakana 115 katakana 114 katakana 113 katakana 112 katakana 111 katakana 110 katakana 109 katakana 108 katakana 107 katakana 106 katakana 105 katakana 104 katakana 103 katakana 102 katakana 101 katakana 100 katakana 99 katakana 98 katakana 97 katakana 96 katakana 95 katakana 94 katakana 93 [00000000] - [10010101] : rom(only luminosity) 7 u 7 pattern no.0 (default) to pattern no.149 rom address map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 41 of 96 product standards zero antenna symbol 124 display contents of the pattern pattern no. symbol 143 ? symbol 142 clock mark symbol 141 symbol 140 o symbol 139 m symbol 138 p symbol 137 n symbol 136 ? symbol 135 ! symbol 134 : symbol 133 = symbol 132 y symbol 131 u symbol 130 symbol 129 + symbol 128 three antenna symbol 127 two antenna symbol 126 one antenna symbol 125 u symbol 144 symbol 145 symbol 146 symbol 147 symbol 148 symbol 149 display contents of the pattern pattern no. [00000000] - [10010101] : rom(only luminosity) 7 u 7 pattern no.0 (default) to pattern no.149 rom address map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 42 of 96 product standards up 3 s gradation 173 square out 1 s gradation 150 display contents of the pattern pattern no. up 2 s gradation 172 up 1 s gradation 171 down 3 s gradation 170 down 2 s gradation 169 down 1 s gradation 168 slant left up 3 s gradation 167 slant left up 2 s gradation 166 slant left up 1 s gradation 165 slant right up 3 s gradation 164 slant right up 2 s gradation 163 slant right up 1 s gradation 162 slant left down 3 s gradation 161 slant left down 2 s gradation 160 slant left down 1 s gradation 159 slant right down 3 s gradation 158 slant right down 2 s gradation 157 slant right down 1 s gradation 156 square in 3 s gradation 155 square in 2 s gradation 154 square in 1 s gradation 153 square out 3 s gradation 152 square out 2 s gradation 151 right 1 s gradation 174 right 2 s gradation 175 right 3 s gradation 176 left 1 s gradation 177 left 2 s gradation 178 left 3 s gradation 179 slant right center 1 s gradation 180 slant right center 2 s gradation 181 slant right center 3 s gradation 182 slant left center 1 s gradation 183 slant left center 2 s gradation 184 display contents of the pattern pattern no. square right down 3 s gradation 194 square right down 2 s gradation 193 square right down 1 s gradation 192 side center 3 s gradation 191 side center 2 s gradation 190 side center 1 s gradation 189 vertical center 3 s gradation 188 vertical center 2 s gradation 187 vertical center 1 s gradation 186 slant left center 3 s gradation 185 [10010110] - [11010000] : rom(luminosity ? cycle ? delay) 7 ? 7 pattern no.150 to pattern no.208 rom address map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 43 of 96 product standards square left down 1 s gradation 195 square left down 2 s gradation 196 square left down 3 s gradation 197 square right up 1 s gradation 198 square right up 2 s gradation 199 square right up 3 s gradation 200 square left up 1 s gradation 201 square left up2 s gradation 202 square left up 3 s gradation 203 square crossing in 1 s gradation 204 square crossing in 2 s gradation 205 square crossing in 3 s gradation 206 square crossing out1 s gradation 207 square crossing out2 s gradation 208 display contents of the pattern pattern no. [10010110] - [11010000] : rom(luminosity ? cycle ? delay) 7 ? 7 pattern no.150 to pattern no.208 rom address map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 44 of 96 product standards firefly 1 s : color 9 color 9 firefly 1 s 21 firefly 1 s : color 10 color 10 firefly 1 s 22 firefly 1 s : color 11 color 11 firefly 1 s 23 firefly 1 s : color 12 color 12 firefly 1 s 24 firefly 1 s : color 8 color 8 firefly 1 s 20 turn on : blue color 1 1 display contents of the pattern pattern no. firefly 1 s : color 7 color 7 firefly 1 s 19 firefly 1 s : color 6 color 6 firefly 1 s 18 firefly 1 s : color 5 color 5 firefly 1 s 17 firefly 1 s : color 4 color 4 firefly 1 s 16 firefly 1 s : color 3 color 3 firefly 1 s 15 firefly 1 s : color 2 color 2 firefly 1 s 14 firefly 1 s : color 1 color 1 firefly 1 s 13 turn on : red + blue + green color 12 12 turn on : between 9 and 10 color 11 11 turn on : red + blue color 10 10 turn on : red color 9 9 turn on : between 7 and 9 color 8 8 turn on : red + green color 7 7 turn on : between 5 and 7 color 6 6 turn on : green color 5 5 turn on : between 3 and 5 color 4 4 turn on : green + blue color 3 3 turn on : between 1 and 3 color 2 2 firefly 2 s : color 1 color 1 firefly 2 s 25 firefly 2 s : color 2 color 2 firefly 2 s 26 firefly 2 s : color 3 color 3 firefly 2 s 27 firefly 2 s : color 4 color 4 firefly 2 s 28 firefly 2 s : color 5 color 5 firefly 2 s 29 firefly 2 s : color 6 color 6 firefly 2 s 30 firefly 2 s : color 7 color 7 firefly 2 s 31 firefly 2 s : color 8 color 8 firefly 2 s 32 display contents of the pattern pattern no. gradation 6 gradation 6 42 gradation 5 gradation 5 41 gradation 4 gradation 4 40 gradation 3 gradation 3 39 gradation 2 gradation 2 38 gradation 1 gradation 1 37 firefly 2 s : color 12 color 12 firefly 2 s 36 firefly 2 s : color 11 color 11 firefly 2 s 35 firefly 2 s : color 10 color 10 firefly 2 s 34 firefly 2 s : color 9 color 9 firefly 2 s 33 [000001] - [101010] : rom(rgb pattern, luminosity ? cycle ? delay )rgb pattern no.1 to no.42 rom address map (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 45 of 96 product standards ? ? tsd cpu wrer frm int ram act ? ? err2eh facgd 1 iofactor r 14h w/r w/r w/r r w/r w w w w r/w iost a2 iosta1 ista3 ista 2 imsk 2 iomsk1 imsk 3 imsk 2 iodet[1:0] idet[1:0] ? ? ? ? iodet 18h iochat2[1:0] iochat1[1:0] ? ? ? ? iochat 17h ichat3[1:0] ichat2[1:0] ichat1[1:0] ? ? ichat 16h ista1 ? ? stagd iostate 15h plcnt[4:0] hien ? ? plcnt 07h lcdsub[4:0] ? ? ? lcdsub 06h lcdmain[4:0] ? ? ? lcdmain 05h data name sub address imsk1 ? ? ? iomsk 12h dds w dco sel osc en vf off ? ? powercnt 01h d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, even if an internal clock or an external clock does not exist, read / write is possible in the data to register. however, it cannot be given to operation finally needed. register table which needs a clock operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 46 of 96 product standards iofac2 iofac 1 ifac3 ifac2 ifac1 ovp scp facgd2 error r 2eh ramnum ? rgbon ? ? ? ? ? ? ? rgbon r/w 2ch rgbdata[5:0] ? ? rgbdata r/w 2dh scltime[1:0] ? ? ? ? ? ? ? scltime r/w 2bh settime[1:0] ? ? ? ? ? ? settime r/w 28h repon ? ? ? ? setto[7:0] setto r/w 26h sclon ? ? ? ? ? ? scroll r/w 2ah ram2 ram1 ? ? ? ? ? ? ramrst r/w 29h ? ? ? ? ? ? ramnum r/w 30h r/w r/w r/w r/w r/w r/w r/w r/w ? ? ? ? ? ? setfrom[7:0] setfrom 25h ? ? repon 27h copy start sel ram ? ? ramcopy 24h selrom[7:0] romsel 23h rom77[1:0] ? ? ? ? ? ffrom 22h data name sub address mtxdata[7:0] mtxdata 21h mtxon ? ? ? ? ? ? ? mtxon 20h d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, even if an inter nal clock or an external clock does not exist, read / write is possible in the data to register. however, it cannot be given to operation finally needed. register table which needs a clock (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 47 of 96 product standards dla1[1:0] fra1[1:0] bla1[3:0] a1 31h dla2[1:0] fra2[1:0] bla2[3:0] a2 32h dla3[1:0] fra3[1:0] bla3[3:0] a3 33h dla4[1:0] fra4[1:0] bla4[3:0] a4 34h dla5[1:0] fra5[1:0] bla5[3:0] a5 35h dla6[1:0] fra6[1:0] bla6[3:0] a6 36h dla7[1:0] fra7[1:0] bla7[3:0] a7 37h dlb1[1:0] frb1[1:0] blb1[3:0] b1 38h dlb2[1:0] frb2[1:0] blb2[3:0] b2 39h dlb3[1:0] frb3[1:0] blb3[3:0] b3 3ah dlb4[1:0] frb4[1:0] blb4[3:0] b4 3bh dlb5[1:0] frb5[1:0] blb5[3:0] b5 3ch dlb6[1:0] frb6[1:0] blb6[3:0] b6 3dh dlb7[1:0] frb7[1:0] blb7[3:0] b7 3eh dlc1[1:0] frc1[1:0] blc1[3:0] c1 3fh dlc2[1:0] frc2[1:0] blc2[3:0] c2 40h dlc3[1:0] frc3[1:0] blc3[3:0] c3 41h dlc4[1:0] frc4[1:0] blc4[3:0] c4 42h dlc5[1:0] frc5[1:0] blc5[3:0] c5 43h dlc6[1:0] frc6[1:0] blc6[3:0] c6 44h dlc7[1:0] frc7[1:0] blc7[3:0] c7 45h dld1[1:0] frd1[1:0] bld1[3:0] d1 46h dld2[1:0] frd2[1:0] bld2[3:0] d2 47h dld3[1:0] frd3[1:0] bld3[3:0] d3 48h dld4[1:0] frd4[1:0] bld4[3:0] d4 49h dld5[1:0] frd5[1:0] bld5[3:0] d5 4ah dld6[1:0] frd6[1:0] bld6[3:0] d6 4bh dld7[1:0] frd7[1:0] bld7[3:0] d7 4ch data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, when an internal clock or an external clock does not exist, data cannot be read / write in at register. register table which needs a clock (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 48 of 96 product standards dlg7[1:0] frg7[1:0] blg7[3:0] g7 61h dlledb1[1:0] dlledg1[1:0] dlledr1[1:0] frledb1[1:0] frledg1[1:0] frledr1[1:0] blledr1[3:0] ledr1 62h blledg1[3:0] ledg1 63h blledb1[3:0] ledb1 64h dle1[1:0] fre1[1:0] ble1[3:0] e1 4dh dle2[1:0] fre2[1:0] ble2[3:0] e2 4eh dle3[1:0] fre3[1:0] ble3[3:0] e3 4fh dle4[1:0] fre4[1:0] ble4[3:0] e4 50h dle5[1:0] fre5[1:0] ble5[3:0] e5 51h dle6[1:0] fre6[1:0] ble6[3:0] e6 52h dle7[1:0] fre7[1:0] ble7[3:0] e7 53h dlf1[1:0] frf1[1:0] blf1[3:0] f1 54h dlf2[1:0] frf2[1:0] blf2[3:0] f2 55h dlf3[1:0] frf3[1:0] blf3[3:0] f3 56h dlf4[1:0] frf4[1:0] blf4[3:0] f4 57h dlf5[1:0] frf5[1:0] blf5[3:0] f5 58h dlf6[1:0] frf6[1:0] blf6[3:0] f6 59h dlf7[1:0] frf7[1:0] blf7[3:0] f7 5ah dlg1[1:0] frg1[1:0] blg1[3:0] g1 5bh dlg2[1:0] frg2[1:0] blg2[3:0] g2 5ch dlg3[1:0] frg3[1:0] blg3[3:0] g3 5dh dlg4[1:0] frg4[1:0] blg4[3:0] g4 5eh dlg5[1:0] frg5[1:0] blg5[3:0] g5 5fh dlg6[1:0] frg6[1:0] blg6[3:0] g6 60h data name sub address d5 d6 d7 data d0 d1 d2 d3 d4 about the following addresses, when an internal clock or an external clock does not exist, data cannot be read / write in at register. register table which needs a clock (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 49 of 96 product standards ? ? ddsw oscen ? default dcosel vfoff ? data name 01h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d3 : vfoff dc/dc converter automatic control selection bit [0] : the automatic control of dc/dc converter is possible. (default) [1] : the automatic control of dc/dc converter is impossible. * the constant current terminal which acts as a monitor is chosen by bl1m, bl2m, bl3m, bl4m, bls1m, and bls2m bit of address 08h at vfoff = low. and if it is less than 0.4 v, dc/dc co nverter will be activated. d2 : oscen the on/off bit for internal oscillators [0] : internal oscillating circuit is off (default) [1] : internal oscillating circuit is on * the variation width of an internal oscillator is set to 0.96mhz - 1.44 mhz. * the variation width of an internal clock is set to 694.4 ns ? 1042 ns. d1 : dcosel dc/dc converter output voltage setup [0] : output voltage set to 4.9 v (default) [1] : output voltage set to 5.3 v d0 : ddsw the on/off bit for dc/dc converter [0] : dc/dc converter is off (default) [1] : dc/dc converter is on * set both bits of ddsw and oscen to [1] to operate dc/dc converter. * make sure to set both bits of oscen and ddsw to [1]. * during oscen = [1] , ddsw must be set to [1]. register map detailed explanation operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 50 of 96 product standards reg28 ? ? ? ? default reg18 ? ? data name 02h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 1 1 0 0 0 d0 d1 d2 d3 d4 d1 : reg18 the on/off control for ldo1(when ldocnt terminal is low) [0] : ldo1 off [1] : ldo1 on (default) d0 : reg28 the on/off control for ldo2( when ldocnt terminal is low ) [0] : ldo2 off [1] : ldo2 on (default) * when ldocnt terminal is high, regardless of the state of reg18, ldo1 will be activated. * when ldocnt terminal is high, regardless of the state of reg28, ldo2 will be activated. * set ldocnt to low after setting re g28 to low to put into off mode. ? 18 n.c. (on) n.c. (on) low ? high high : on at standby mode low : off high : on <1 (off mode) or 8 (standby mode) 18 <1 itotal typ(ma) low : off at off mode n.c. (on) off reg28 * n.c. (off) high ? low * n.c. (on) high * off low (initial condition) note reg18 ldocnt note) * : explanation in each mode (power supply starting sequence) of page 26. refer to the note. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 51 of 96 product standards sersel ? ? ? ? default ? ? ? data name 03h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : sersel the serial interface change which controls lcdmain luminosity control. [0] : gpio operation (default) [1] : serial control of address 05h (lcdmain) by spi2 * gpi1 to gpi3 terminals serve as an input setup and an interruption mask compulsorily at sersel = high setup. spi1 spi2 reg 05h constant current circuit lcdmain sersel blsdat operation gpi3 operation gpi3 terminal spi2 operation blsclk operation blsce operation 1 gpio operation gpi2 operation gpi1 operation 0 operation gpi2 terminal gpi1 terminal sersel register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 52 of 96 product standards default lsiver[7:0] data name 04h r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : lsiver[7:0] the register showing the version of lsi [00000000] : es1 [00000001] : es2 : : register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 53 of 96 product standards lcdmain[4:0] ? ? default ? data name 05h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d4-0 : lcdmain[4:0] output current setup of bl1-bl4 terminal [00000] : 0 ma (default) [00001] : 1 ma [00010] : 2 ma : : [11110] : 30 ma [11111] : 31 ma the waveform of main lcd backlights current of operation * as for main lcd backlights part, output current changes stepwise for noise reduction. * by the time it reaches current setup value, there will be delay of setup value ? internal 32clk. * when internal clk stops during state trans ition, the state at that time is held. * the following waveform is internal signal. 32clk (typ26.6 ? s) 00000 00001 00010 00011 00100 00101 00110 00111 01000 00000 ? 01000 01000 ? 00011 internal luminosity set point signal t 32clk ? 8step register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 54 of 96 product standards lcdsub[4:0] ? ? default ? data name 06h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d4-0 : lcdsub[4:0 ] output current setup of bls1 - bls2 terminal. [00000] : 0 ma (default) [00001] : 1 ma [00010] : 2 ma : : [11110] : 30 ma [11111] : 31 ma * d7, d6, and d5 must not be written. the waveform of sub lcd backlights current of operation 32clk (typ26.6 ? s) 00000 00001 00010 00011 00100 00101 00110 00111 01000 00000 ? 01000 01000 ? 00011 t 32clk ? 8step internal luminosity set point signal * as for sub lcd backlights part, output current changes stepwise for noise reduction. * by the time it reaches current setup value, there will be delay of setup value ? internal 32clk. * when internal clk stops during state trans ition, the state at that time is held. * the following waveform is internal signal. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 55 of 96 product standards plcnt[4:0] hien ? default ? data name 07h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d5 : hien current large mode on/off control of pl1 - pl2 terminal. [0] : off (default) [1] : on (+30 ma) d4-0 : plcnt[4:0] ou tput current setup of pl1 - pl2 terminal. [00000] : 0 ma (default) [00001] : 1 ma [00010] : 2 ma : : [11110] : 30 ma [11111] : 31 ma the waveform of photo flashes current of operation 32clk (typ26.6 ? s) 00000 00001 00010 00011 00100 00101 00110 00111 01000 00000 ? 01000 01000 ? 00011 t 32clk ? 8step internal luminosity set point signal * as for photo flashes part, output current changes stepwise for noise reduction. * by the time it reaches current setup value, there will be delay of setup value ? internal 32clk. * when internal clk stops during state transition, the state at that time is held. * the following waveform is internal signal. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 56 of 96 product standards pwmclk bls2m bls1m bl4m bl3m bl2m bl1m default ? data name 08h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d6 : bl1m the automatic on control monitor selection bit of dc/dc converter. (bl1 terminal) [0] : monitor of bl1 terminal is possible.(default) [1] : monitor of bl1 terminal is impossible. d5 : bl2m the automatic on control monitor selection bit of dc/dc converter. (bl2 terminal) [0] : monitor of bl2 terminal is possible.(default) [1] : monitor of bl2 terminal is impossible. d4 : bl3m the automatic on control monitor selection bit of dc/dc converter. (bl3 terminal) [0] : monitor of bl3 terminal is possible.(default) [1] : monitor of bl3 terminal is impossible. d3 : bl4m the automatic on control monitor selection bit of dc/dc converter. (bl4 terminal) [0] : monitor of bl4 terminal is possible.(default) [1] : monitor of bl4 terminal is impossible. d2 : bls1m the automatic on control monitor selection bit of dc/dc converter. (bls1 terminal) [0] : monitor of bls1 terminal is possible.(default) [1] : monitor of bls1 terminal is impossible. d1 : bls2m the automatic on control monitor selection bit of dc/dc converter. (bls2 terminal) [0] : monitor of bls2 terminal is possible.(default) [1] : monitor of bls2 terminal is impossible. d0 : pwmclk the pwm operation clock selection bit. [0] : it operates by an internal clock. (default) [1] : it operates by an extclk clock. * interruption of address 14h is generated only in the oscen = high state at pwmclk = low. * interruption of address 14h is generated only in the state where a clock is input into extclk terminal, at pwmclk = high register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 57 of 96 product standards vibrgb2 vibrgb1 vibmtx vibsub2 vibsub1 vibpl2 vibpl1 default vibact data name 09h w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : vibact a putting-out-lights setup of led by vibctl terminal. [0] : the light is switched on at vibctl = low.(default) [1] : the light is switched on at vibctl = high. d6 : vibpl1 a putting-out-lights on/off setup of pl1 terminal by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. d5 : vibpl2 a putting-out-lights on/off setup of pl2 terminal by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. d4 : vibsub1 a putting-out-lights on/off setup of bls1 terminal by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. d3 : vibsub2 a putting-out-lights on/off setup of bls2 terminal by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. d2 : vibmtx a putting-out-lights on/off setup of 7*7 dots matrix led by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. d1 : vibrgb1 a putting-out-lights on/off setup of r1, g1 and b1 terminal by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. d0 : vibrgb2 a putting-out-lights on/off setup of r2, g2 and b2 terminal by vibctl terminal. [0] : putting-out-lights control off by vibctl terminal. (default) [1] : putting-out-lights contro l on by vibctl terminal. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 58 of 96 product standards disrgb2 disrgb1 dismtx dissub2 dissub1 displ2 displ1 default ledact data name 0ah w 0 d5 w 0 d6 w 0 d7 data mode sub address w w w w w 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : ledact a putting-out-lights setup of led by ledctl terminal. [0] : the light is switched on at ledctl = low(default) [1] : the light is switched on at ledctl = high d6 : displ1 a putting-out-lights on/off setup of pl1 terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d5 : displ2 a putting-out-lights on/off setup of pl2 terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d4 : dissub1 a putting-out-lights on/off setup of bls1 terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d3 : dissub2 a putting-out-lights on/off setup of bls2 terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d2 : dismtx a putting-out-lights on/off setup of 7*7 dots matrix led by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d1 : disrgb1 a putting-out-lights on/off setup of r1, g1 and b1 terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. d0 : disrgb2 a putting-out-lights on/off setup of r2, g2 and b2 terminal by ledctl terminal. [0] : putting-out-lights control off by ledctl terminal. (default) [1] : putting-out-lights control on by ledctl terminal. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 59 of 96 product standards 0ma off 1 1 0 off is plcnt[4:0] = [00000] by plcnt[4:0] on 1 0 0 on off on on on on pl1 control signal off is plcnt[4:0] = [00000] by plcnt[4:0] 0 0 1 off is plcnt[4:0] = [00000] by plcnt[4:0] 0 1 0 off is plcnt[4:0] = [00000] by plcnt[4:0] 0 0 0 off is plcnt[4:0] = [00000] by plcnt[4:0] 1 1 1 0ma 1 0 1 off is plcnt[4:0] = [00000] by plcnt[4:0] 0 1 1 current value vibpl1 vibact vibctl 0ma off 1 1 0 off is plcnt[4:0] = [00000] by plcnt[4:0] on 1 0 0 on off on on on on pl1 control signal off is plcnt[4:0] = [00000] by plcnt[4:0] 0 0 1 off is plcnt[4:0] = [00000] by plcnt[4:0] 0 1 0 off is plcnt[4:0] = [00000] by plcnt[4:0] 0 0 0 off is plcnt[4:0] = [00000] by plcnt[4:0] 1 1 1 0ma 1 0 1 off is plcnt[4:0] = [00000] by plcnt[4:0] 0 1 1 current value displ1 ledac t ledctl * when control signal is input from both vibctl termina l and ledctl terminal, the off state of each pl1 terminal control signal is processed in or logic. * same control for vibpl2 and pl2 terminal * same control for vibsub1 and bls1 terminal * same control for vibsub2 and bls2 terminal * same control for vibmtx and x0 - x6 terminal * same control for vibrgb1 and r1, g1 and b1 terminal * same control for vibrgb2 and r2, g2 and b2 terminal * same control for displ2 and pl2 terminal * same control for dissub1 and bls1 terminal * same control for dissub2 and bls2 terminal * same control for dismtx and x0 - x6 terminal * same control for disrgb1 and r1, g1 and b1 terminal * same control for disrgb2 and r2, g2 and b2 terminal ex.)in the case of pl1 terminal register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 60 of 96 product standards gpioclk ? ? ? ? ? ? default ? data name 10h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : gpioclk change of the clock for gpio control. [0] : it operates by an internal clock. (default) [1] : it operates by an extclk clock. * at gpioclk = low, register (iofactor, iostate, ichat, iochat), interruption of address 2eh, and int terminal operate in the state of oscen = high. * at gpioclk = high, register (iofactor, iostate, ichat, iochat), interruption of address 2eh, and int terminal operate, where clock is input into extclk terminal. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 61 of 96 product standards iosel2 iosel1 ? ? ? ? ? default ? data name 11h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1 : iosel1 an input/output setup of gpio1 terminal [0] : input (default) [1] : output d0 : iosel2 an input/output setup of gpio2 terminal [0] : input (default) [1] : output register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 62 of 96 product standards iomsk2 iomsk1 imsk3 imsk2 imsk1 ? ? default ? data name 12h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d4 : imsk1 gpi1 terminal change-of-state detection mask setup. [0] : interruption output mask (default) [1] : interruption output enable * the mask of the interruption detection output ista1 by change-of-state detection of gpi1 terminal is carried out. d3 : imsk2 gpi2 terminal change-of-state detection mask setup. [0] : interruption output mask (default) [1] : interruption output enable * the mask of the interruption detection output ista2 by change-of-state detection of gpi2 terminal is carried out. d2 : imsk3 gpi3 terminal change-of-state detection mask setup. [0] : interruption output mask (default) [1] : interruption output enable * the mask of the interruption detection output ista3 by change-of-state detection of gpi3 terminal is carried out. d1 : iomsk1 gpio1 terminal change-of-state detection mask setup. [0] : interruption output mask (default) [1] : interruption output enable * the mask of the interruption detection output iosta1 by change-of-state detection of gpio1 terminal is carried out. d0 : iomsk2 gpio2 terminal change-of-state detection mask setup. [0] : interruption output mask (default) [1] : interruption output enable * the mask of the interruption detection output iosta2 by change-of-state detection of gpio2 terminal is carried out. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 63 of 96 product standards ioout2 ioout1 oout2 oout1 ? ? ? default ? data name 13h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d3 : oout1 an output logic setup of gpo1 terminal [0] : output is low (default) [1] : output is high d2 : oout2 an output logic setup of gpo2 terminal [0] : output is low (default) [1] : output is high d1 : ioout1 an output logic setup of gpio1 terminal [0] : output is low (default) [1] : output is high * effective only at iosel1 = high (output mode). d0 : ioout2 an output logic setup of gpio2 terminal [0] : output is low (default) [1] : output is high * effective only at iosel2 = high (output mode). register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 64 of 96 product standards tsd cpuwrer frmint ramact ? ? err2eh default facgd1 data name 14h r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : facgd1 [0] : normal operation (default) [1] : no read clearance d6 : err2eh unusual detection of address 2eh 0 : it is not unusual detection to address 2eh. (default) 1 : it is unusual detection to address 2eh. read to address 2eh. d3 : ramact internal ram access judgment 0 : ram is not accessed. (default) 1 : ram is accessed. d2 : frmint an one-frame display end judging scroll on display. 0 : under a frame display (default) 1 : frame display end d1 : cpuwrer cpu access error judgment 0 : cpu access error does not occur. (default) 1 : cpu access error occurs. d0 : tsd unusual detection of tsd error. 0 : tsd unusual detection does not occur. (default) 1 : tsd unusual detection occurs. * the write contents from cpu are not reflected in this ic at cpuwrer = high. write from cpu again. * the interval of facgd1 = high is maximum 1.93 ? s (at the internal clock operation) from the renewal time of data. * at facgd1 = low, if address 14h data is read, data of d0 - d6 are cleared. * ram access from cpu cannot be performed at ramact = high . * when each address 14h register is set to high, t he pulse in a cycle of 4 ms is output from int. * the pulse output from int continues an output until address 14h is read. * the pulse output from int continues an output until address 2eh is also read in err2eh = high . * the states for ramact = high are shown below. 1. while copying to ram from rom. 2. while clearing ram register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 65 of 96 product standards iosta2 iosta1 ista3 ista2 ista1 ? ? default stagd data name 15h r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : stagd [0] : normal operation (default) [1] : data interruption disregard d4 : ista1 the state after chattering removal of gpi1 terminal. [0] : the terminal state after chattering is 0. (default) [1] : the terminal state after chattering is 1. d3 : ista2 the state after chattering removal of gpi2 terminal. [0] : the terminal state after chattering is 0. (default) [1] : the terminal state after chattering is 1. d2 : ista3 the state after chattering removal of gpi3 terminal. [0] : the terminal state after chattering is 0. (default) [1] : the terminal state after chattering is 1. d1 : iosta1 the state after chattering removal of gpio1 terminal. [0] : the terminal state after chattering is 0. (default) [1] : the terminal state after chattering is 1. d0 : iosta2 the state after chattering removal of gpio2 terminal. [0] : the terminal state after chattering is 0. (default) [1] : the terminal state after chattering is 1. * the interval of stagd = high is maximum 1.93 ? s (at internal clock operation) from the time at which data was updated. * at iosel1 = high or iosel2 = high, th e data of ioout1 or ioout2 is stored. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 66 of 96 product standards ichat3[1:0] ichat2[1:0] ichat1[1:0] ? default ? data name 16h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d5-4 : ichat1[1:0] an interruption chattering processing time setup of gpi1 terminal. [00] : 4800clk ? 0 no chattering processing time (default) [01] : 4800clk ? (4-1) chattering processing time is 10.58 ms to 18.47 ms [10] : 4800clk ? (9-1) chattering processing time is 28.23 ms to 41.54 ms [11] : 4800clk ? (16-1) chattering processing time is 52.94 ms to 73.85 ms d3-2 : ichat2[1:0] an interruption chattering processing time setup of gpi2 terminal. [00] : 4800clk ? 0 no chattering processing time (default) [01] : 4800clk ? (4-1) chattering processing time is 10.58 ms to 18.47 ms [10] : 4800clk ? (9-1) chattering processing time is 28.23 ms to 41.54 ms [11] : 4800clk ? (16-1) chattering processing time is 52.94 ms to 73.85 ms d1-0 : ichat3[1:0] an interruption chattering processing time setup of gpi3 terminal. [00] : 4800clk ? 0 no chattering processing time (default) [01] : 4800clk ? (4-1) chattering processing time is 10.58 ms to 18.47 ms [10] : 4800clk ? (9-1) chattering processing time is 28.23 ms to 41.54 ms [11] : 4800clk ? (16-1) chattering processing time is 52.94 ms to 73.85 ms *the times shown above are for when the internal clock operates. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 67 of 96 product standards ? iochat2[1:0] iochat1[1:0] ? ? default ? data name 17h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d3-2 : iochat1[1:0] an interruption chattering processing time setup of gpio1 terminal. [00] : 4800clk ? 0 no chattering processing time (default) [01] : 4800clk ? (4-1) chattering processing time is 10.58 ms to 18.47 ms [10] : 4800clk ? (9-1) chattering processing time is 28.23 ms to 41.54 ms [11] : 4800clk ? (16-1) chattering processing time is 52.94 ms to 73.85 ms d1-0 : iochat2[1:0] an interruption chattering processing time setup of gpio2 terminal. [00] : 4800clk ? 0 no chattering processing time (default) [01] : 4800clk ? (4-1) chattering processing time is 10.58 ms to 18.47 ms [10] : 4800clk ? (9-1) chattering processing time is 28.23 ms to 41.54 ms [11] : 4800clk ? (16-1) chattering processing time is 52.94 ms to 73.85 ms *the times shown above are for when the internal clock operates. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 68 of 96 product standards ? iodet[1:0] idet[1:0] ? ? default ? data name 18h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d3-2 : idet[1:0] the interruption detection method setup of gpi1, gpi2 and gpi3 terminal. [00] : change-of-state detection is impossible. (default) [01] : change of the terminal st ate from low to high is detected. [10] : change of the terminal st ate from high to low is detected. [11] : both the edge of change of a terminal state is detected. (low ? high and high ? low ) d1-0 : iodet[1:0] the interruption detection method setup of gpio1 and gpio2 terminal. [00] : change-of-state detection is impossible. (default) [01] : change of the terminal st ate from low to high is detected. [10] : change of the terminal st ate from high to low is detected. [11] : both the edge of change of a terminal state is detected. (low ? high and high ? low ) register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 69 of 96 product standards ioplud2 b2on r2on ioplud1 g2on ? ? default ? data name 19h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d4 : r2on on/off cont rol of r2 terminal [0] : off (default) [1] : on d3 : g2on on/off c ontrol of g2 terminal [0] : off (default) [1] : on d2 : b2on on/off control of b2 terminal [0] : off (default) [1] : on d1 : ioplud1 a terminal processing setup of gpio1 terminal [0] : pull-up processing (default) [1] : not pull-up processing d0 : ioplud2 a terminal processing setup of gpio2 terminal [0] : pull-up processing (default) [1] : not pull-up processing * ioplud1 and ioplud2 are effective only when iosel1 and iosel2 are input modes. * in the case of the state of ioplud1 = low and iovsel1 = high, the power of 2.85 v cannot be applied to gpio1. * in the case of the state of ioplud2 = low and iovse l2 = high, the power of 2.85 v cannot be applied to gpio2. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 70 of 96 product standards iovsel2 ovsel2 ? iovsel1 ovsel1 ? ? default intvsel data name 1ah w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : intvsel a terminal voltage setup of int terminal [0] : 1.85 v (default) [1] : 2.85 v d3 : ovsel1 a terminal voltage setup of gpo1 terminal [0] : 2.85 v (default) [1] : 1.85 v d2 : ovsel2 a terminal voltage setup of gpo2 terminal [0] : 2.85 v (default) [1] : 1.85 v d1 : iovsel1 a terminal voltage setup of gpio1 terminal [0] : 2.85 v (default) [1] : 1.85 v d0 : iovsel2 a terminal voltage setup of gpio2 terminal [0] : 2.85 v (default) [1] : 1.85 v register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 71 of 96 product standards mtxon ? ? ? ? ? ? default ? data name 20h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : mtxon an on/off setup of matrix led [0] : off (default) [1] : on * during mtxon = high, subsequent rom, ram, and the contro l contents to a register are sequentially processed and lit up. * when address 08h pwmclk is low, set mtxon to high 5 ms after setting address 01h oscen to high. * when address 08h pwmclk is high, set mtxon to hi gh 5 ms after inputting cl ocks to extclk terminal. * set mtxon to high, and then set up other addresses to display the matrix part. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 72 of 96 product standards default mtxdata[7:0] data name 21h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : mtxdata[7:0] an address setup of rom/ram of the data to read [00000000] - [10010101] : rom ( only luminosity ) 7*7 pattern no.0 (d efault) to no.149 [10010110] - [11010000] : rom ( luminosity ? cycle ? delay ) 7*7 pattern no. 150 to no.208 [11010001] - [11010010] : ram ( luminosity ? cycle ? delay ) 7*7 pattern ram no.1, 2 * the pattern no.0 of rom is all 0 data of matrix led. * accessing to 21h is disabled while copying from rom to ram (copystart = high of 24h). register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 73 of 96 product standards ? rom77[1:0] ? ? ? ? default ? data name 22h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : rom77[1:0] lighting control of the 7x7 (led no.a1-g7) fixed pattern of rom [00] : rom data is displayed. [01] : rom data is displayed by firefly lighting in 1 s. [10] : rom data is displayed by firefly lighting in 2 s. [11] : rom data is displayed by firefly lighting in 3 s. * during display of repetition (repon = high), rom77 must not be changed. a b c d efg 1 2 3 4 5 6 7 t t1 t3 t2 t4 t1 = t2 = t4 = 249.2 ms t3 = 265.8 ms the peak value of luminosity is a value set up by rom. luminosity firefly lighting cycle : t led?s number led?s number register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 74 of 96 product standards default selrom[7:0] data name 23h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : selrom[7:0] an address setup of rom copied to ram. [00000000] - [10010101] : rom (only luminosity) 7*7 pattern no.0 (default) to no.149 [10010110] - [11010000] : rom (luminosity ? cycle ? delay) 7*7 pattern no.150 to no.208 * accessing to 23h is disabled while copying from rom to ram (copystart = high of 24h). register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 75 of 96 product standards ? ?? ? selram copystart ? default ? data name 24h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1 : selram a ram number setup of a copy place. 0 : ram no.1 1 : ram no.2 d0 : copystart copy start on/off control to ram from rom [0] : off [1] : the copy set up by selrom and selram is started. (it returns to 0 by internal 51 clk.) * address 24h is only for copying data to ram and never start led display. (however, if this ram is copied when led display is showing, led display is updated.) * writing in address 21h-mtxdata, 2ah-sclon, and 27h-repon is disabled while copying. (ramact flag is raised.) * accessing to selram is disabled while copyi ng from rom to ram (copystart = high of 24h) * don?t write address 29h (ram-clear ) while copying. (the waiting time for 1 ms or more is required after copystart.) register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 76 of 96 product standards default setfrom[7:0] data name 25h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : setfrom[7:0] an address setup of the rom frame data at the repetition display start. [00000000] - [10010101] : rom (only luminosity) 7*7 pattern no.0 (default) to no.149 [10010110] - [11010000] : rom (luminosity ? cycle ? delay) 7*7 pattern no.150 to no.208 * during display of repetition (repon = high), don?t change the setting of setfrom. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 77 of 96 product standards default setto[7:0] data name 26h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : setto[7:0] an address setup of the rom frame data at the repetition display end. [00000000] - [10010101] : rom (only luminosity) 7*7 pattern no.0 (default) to no.149 [10010110] - [11010000] : rom (luminosity ? cycle ? delay) 7*7 pattern no.150 to no.208 * during display of repetition (repon = high), don?t change the setting of setto. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 78 of 96 product standards repon ? ? ? ? ? ? default ? data name 27h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : repon repetition display on/off control 0 : repetition display off (default) 1 : repetition display on * during display of repetition, display of set-up rom is continued. * a repetition display is started in the state of mtxon = high and repon = high. * accessing to 27h is disabled while copying from rom to ram (copystart = high of 24h). * when the setting of sclon is changed from low to high while repon = high, repon becomes low and it shifts to scroll function. * during display of repetition (repon = high), don?t change the setting of setfrom and setto. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 79 of 96 product standards settime[1:0] ? ? ? ? ? default ? data name 28h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : settime[1:0] a frame display time setup of repetition display [00] : 1 s (default) [01] : 2 s [10] : 3 s [11] : 4 s register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 80 of 96 product standards ram2 ram1 ? ? ? ? ? default ? data name 29h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1 : ram1 the data in 7*7 ram1 is cleared. 0 : overwrite is possible. (default) 1 : the data in 7*7 ram1 is cleared. (it returns to 0 by internal 2 clk.) d0 : ram2 the data in 7*7 ram2 is cleared. 0 : overwrite is possible. (default) 1 : the data in 7*7 ram2 is cleared. (it returns to 0 by internal 2 clk.) * don?t set the ram-clear operation for ram1 or ram2 during display of repetition (sclon = high). * don?t set the ram-clear operation (29h) during the copy operation (24h). (the waiting time for 1 ms or mo re is required after copystart.) register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 81 of 96 product standards ? ?sclon ? ? ? ? default ? data name 2ah w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : sclon on/off setup of scroll display 0 : off (default) 1 : on * a scroll display displays the data which exists in the ram no.1 -2 of 7*7 in order of a-g column. the display travel time of a column is the preset value of scltime. * during display of scroll, data can be written to ram without specifying ram number. (writing is performed to empty ram.) * a scroll display is started in the state of mtxon = high and sclon. * accessing to 2ah is disabled while copying from rom to ram (copystart = high of 24h). * when the setting of repon is changed from low to high while sclon = high, sclon becomes low and it shifts to repetition display function. * during display of scroll (sclon = high), don?t change the setting of ram1 and ram2. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 82 of 96 product standards scltime[1:0] ?? ? ? ? default ? data name 2bh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : scltime[1:0] a frame display time setup of scroll display [00] : 0.1 s (default) [01] : 0.2 s [10] : 0.4 s [11] : 0.8 s * the display travel time of the column is the preset value of scltime. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 83 of 96 product standards ? ? rgbon ? ? ? ? default ? data name 2ch w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d0 : rgbon on/off setup of rgb lighting 0 : off (default) 1 : on * when address 08h pwmclk is low, set rgbon to high 5 ms after setting address 01h oscen to high. * when address 08h pwmclk is high, set rgbon to high 5 ms after inputting clo cks to extclk terminal. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 84 of 96 product standards rgbdata ? default ? data name 2dh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-0 : rgbdata[5:0] an address setup of rom and register which read rgb data [000000] : register is displayed. [000001] - [101010] : rom (rgb pattern, luminosity ? cycle ? delay) pattern no.1 to no.42 register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 85 of 96 product standards iofac2 iofac1 ifac3 ifac2 ifac1 ovp scp default facgd2 data name 2eh r 0 d5 r 0 d6 r 0 d7 data mode sub address r r r r r 0 0 0 0 0 d0 d1 d2 d3 d4 d7 : facgd [0] : normal operation (default) [1] : no read clearance d6 : scp an interruption factor register when short comparator operates while the dc/dc converter operated. [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. d5 : ovp an interruption factor register when over-volt age detection comparator operates while the dc/dc converter operated. [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. d4 : ifac1 the interruption factor register of gpi1 terminal [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. d3 : ifac2 the interruption factor register of gpi2 terminal [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. d2 : ifac3 the interruption factor register of gpi3 terminal [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. d1 : iofac1 the interruption factor register of gpio1 terminal [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. d0 : iofac2 the interruption factor register of gpio2 terminal [0] : an interrupt does not occur. (default) [1] : an inte rrupt occurs. * the interval of facgd2 = high is maximum 1.93 ? s (at internal clock operation) from the renewal time of data. * at facgd2 = low, if the data of address 2eh is read, data of d0 - d6 are cleared. * only at iosel1 = low or iosel2 = low, an interruption factor is generated. * in the case of iosel1 = high or iosel2 = high, status and register in chattering removal circuit is reset. * when each address 2eh register is set to high, t he pulse in a cycle of 4 ms is output from int. * the pulse output from int continues an output until address 14h is read. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 86 of 96 product standards ramnum ? ? ? ? ? ? default ? data name 30h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d1-0 : ramnum[1:0] a ram number setup at the cpu access (read and write). 0 : ram no.1 1 : ram no.2 * accessing to 30h is disabled during display of scroll (2ah sclon = high). register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 87 of 96 product standards dla1[1:0] fra1[1:0] default bla1[1:0] data name 31h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-4 : bla1[1:0] luminosity setup of led no.a1 [0000] : 0 ma (default) [0001] : 1 ma [0010] : 2 ma [0011] : 3 ma [0100] : 4 ma [0101] : 5 ma [0110] : 8 ma [0111] : 11 ma [1000] : 15 ma [1001] : 17 ma [1010] : 19 ma [1011] : 21 ma [1100] : 24 ma [1101] : 26 ma [1110] : 28 ma [1111] : 30 ma d3-2 : fra1[1:0] firefly operation and cycle setup of the led no.a1 [00] : lighting mode (default) [01] : firefly lighting cycle 1 s [10] : firefly lighting cycle 2 s [11] : firefly lighting cycle 3 s d1-0 : dla1[1:0] firefly operation delay setup of the led no.a1 [00] : no delay (default) [01] : delay 25 % [10] : delay 50 % [11] : delay 75 % * the operation is the same as above for the addresses to 61h corresponding to each led number. * the waiting time for 2 or more internal clocks (2 ? s or more) is required after the data from address 31h to 61h is written in. please input other serial commands after that. a b c d efg 1 2 3 4 5 6 7 led?s number led?s number register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 88 of 96 product standards dlledr1[1:0] frledr1[1:0] default blledr1[1:0] data name 62h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 d7-4 : blledr1[1:0] luminosity setup of r1 terminal [0000] : 0 ma (default) [0001] : 1 ma [0010] : 2 ma : : [1110] : 14 ma [1111] : 15 ma d3-2 : frledr1[1:0] firefly operat ion and cycle setup of r1 terminal [00] : lighting mode (default) [01] : firefly lighting cycle 1 s [10] : firefly lighting cycle 2 s [11] : firefly lighting cycle 3 s d1-0 : dlledr1[1:0] firefly operation delay setup of r1 terminal [00] : no delay (default) [01] : delay 25 % [10] : delay 50 % [11] : delay 75 % * the operation is the same as above for the addresses to 67h corresponding to g1 and b1 terminal. * the waiting time for 2 or more internal clocks (2 ? s or more) is required after the data from address 62h to 64h is written in. please input other serial commands after that. register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 89 of 96 product standards prot1 ? ? ? ? ? ? default ? data name 6bh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 6bhd0(prot1), 6dhd4(prot2), 6fhd7(prot3) * please don?t access to address 6bh to 6fh. * addresses to 77h are for test. * when all the three above bits are set to high, it is allowed to write in addresses [ 70h - 77h ]. (for test. do not setup these addresses.) d7-0 : test1[7:0] the register for test * addresses to 77h are for test. * please don?t access to address 70h to 77h. ? ? ? ? prot2 ? ? default ? data name 6dh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 ? ? ? ? ? ? ? default prot3 data name 6fh w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 default test1[7:0] data name 70h w/r 0 d5 w/r 0 d6 w/r 0 d7 data mode sub address w/r w/r w/r w/r w/r 0 0 0 0 0 d0 d1 d2 d3 d4 register map detailed explanation (continued) operation (continued) 4. register and address (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 90 of 96 product standards ? the interface with microcomputer consists of 16 bit-serial register (8-bit of command, 8-bit of address), and address decoder and transmitting register (8-bit). ? serial interface consists of four terminals of serial clock terminal (clk), serial-data input terminal (di), serial- data output terminal (do), and chip enable input terminal (ce). clk di w d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 ce do hi-z clk do ce di d0 d1 d2 d3 d4 d5 d6 d7 ra0 a1 a2 a3 a4 a5 a6 hi-z hi-z (1) reception operation ? data is taken into internal shift register by the rising edge of clk. (a maximum of 13 mhz of frequency of clk can be used) ? in high interval of ce, reception of data becomes enable. (active : high) ? data is transmitted at msb first in order of a control register address (8-bit) and control command (8-bit). timing of reception (2) transmission operation ? data is taken into internal shift register by the rising edge of clk. (a maximum of 6 mhz of frequency of clk can be used) * it is not possible to read ram data. ? in high interval of ce, reception of data becomes enable. (active : high) ? data is transmitted at msb first in order of a control register address (8-bit) and control command (max 8-bit). timing of transmission spi1 format operation (continued) 5. serial interface format d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 91 of 96 product standards ldo1 bgr tsd vb vbled vbdcdc ldo2 ldo2 ldo1 logic i/o bgr tsd vled1 vled2 agnd dgnd dcdcgnd pgnd2 pgnd1 ledgnd1 ledgnd2 rgbgnd2 rgbgnd1 dcdc chgsw bl bls pl mtx rgb scan power supply distribution diagram operation (continued) 6. signal distribution diagram d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 92 of 96 product standards oscillator 1.2mhz selector 1 0 (pad) extclk (register) pwmclk selector 1 0 (register) gpioclk regmap gpio matrix rgb * step change of states of output current 05h lcdmain 06h lcdsub 07h plcnt * matrix, rgb operation pwm control read / write of memory data (rom and ram) 14h ramact, frmint, cpuwrer * gpio operation 4 ms sampling control 4 ms pulse control of interruption 14h interruption generating 2eh interruption generating spi1 (pad) clk (pad) csb (pad) di selector 1 0 (register) sersel (pad) gpi1 spi2 (pad) gpi2 (pad) gpi3 blsclk blsdat blsce (pad) do *serial ? parallel conversion sclk serial ? parallel conversion (input) sclk_n parallel o serial conversion (output) regclk serial o parallel conversion output is latched in a standup. * serial ? parallel conversion only 05h blsclk serial o parallel conversion (input) regclk2 serial o parallel conversion output is latched in a standup. sclk sclk_n regclk regclk2 control / clock distribution diagram operation (continued) 6. signal distribution diagram (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 93 of 96 product standards dla1[1:0] fra1[1:0] bla1[1:0] 0 0 0 0 00 0 1 dla1[1:0] fra1[1:0] bla1[1:0] 0 1 1 1 10 0 1 dla1[1:0] fra1[1:0] bla1[1:0] 0 0 1 1 10 1 1 dla1[1:0] fra1[1:0] bla1[1:0] 1 0 1 1 10 1 1 33 ma t firefly lighting cycle t2 = 2.0268 s fra1 = [10] a1 dla1 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms a1 19 ma t firefly lighting cycle t = 1.0134 s fra1 = [01] a1 33 ma t firefly lighting cycle t2 = 2.0268 s fra1 = [10] a1 bla1 = [1000] bla1 = [1111] t 33 ma bla1 = [1111] bla1 = [1111] example of initial setting for lighting current value serial on firefly lighting setup 1 s current value serial on serial on serial on current value current value change to cycle 1 s to 2 s change to delay 0 ? 25 % example of firefly lighting 1 operation (continued) 7. example of firefly lighting d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 94 of 96 product standards t firefly lighting cycle t1 = 3.0402 s fra1 = [11] t1 t3 t2 t4 t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms bla1 a1 t firefly lighting cycle t2 = 2.0268s frc5 = [10] blc5 c5 t firefly lighting cycle t3 = 1.0134 s frf3 = [01] t9 = t10 = t12 = 249.2 ms t11 = 265.8 ms blf3 f3 dlc5 = [01] t5 t6 t7 t8 t5 = t6 = t8 = 498.4 ms t7 = 531.6 ms dlf3 = [10] t9 t10 t11 t12 t firefly lighting cycle t1 = 3.0402 s fre7 = [11] t1 t3 t2 t4 ble7 e7 dle7 = [11] t1 = t2 = t4 = 747.6 ms t3 = 797.4 ms luminosity luminosity luminosity luminosity example of firefly lighting 2 operation (continued) 7. example of firefly lighting (continued) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 95 of 96 product standards package information ( reference data ) d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
AN32055A page 96 of 96 product standards important notice 1. when using the lsi for new models, verify the safety including the long-term reliability for each product. 2. when the application system is designed by using this lsi, please confirm the notes in this book. please read the notes to descriptions and the usage notes in the book. 3. this lsi is intended to be used for general electronic equipment. consult our sales staff in advance for information on the following applications: special applications in which exceptional quality and reliab ility are required, or if the failure or malfunction of this lsi may directly jeopardize life or harm the human body. any applications other than the standard applications intended. (1) space appliance (such as artificial satellite, and rocket) (2) traffic control equipment (such as for automobile, airplane, train, and ship) (3) medical equipment for life support (4) submarine transponder (5) control equipment for power plant (6) disaster prevention and security device (7) weapon (8) others : applications of which reliability equivalent to (1) to (7) is required our company shall not be held responsible for any damage incurred as a result of or in connection with the lsi being used for any special application, unless our company agrees to the use of such special application. 4. this lsi is neither designed nor intended for use in automotive applications or environments unless the specific product is designated by our company as compliant with the iso/ts 16949 requirements. our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in connection with the lsi being used in automotive application, unless our company agrees to such application in this book. 5. please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of control led substances, including without limitation, the eu rohs directive. our company shall not be held responsible for any damage incurred as a result of our lsi being used by our customers, not complying with the applicable laws and regulations. 6. pay attention to the direction of lsi. when mounting it in the wrong direction onto the pcb (printed-circuit-board), it migh t emit smoke or ignite. 7. pay attention in the pcb (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins . in addition, refer to the pin description for the pin configuration. 8. perform visual inspection on the pcb before applying power, otherwise damage might happen due to problems such as solder-bridge between the pins of the semiconductor device. also, perform full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the lsi during transportation. 9. take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs such as output pin-vcc short (power supply fault), output pin-gnd short (ground fault), or output-to-output-pin short (load short). safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capab ility of the power supply. 10. the protection circuit is for maintaining safety against abnormal operation. therefore, the protection circuit should not w ork during normal operation. especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to vcc short (power supply fault), or output pin to gnd short (ground fault), the lsi might be damaged before the thermal protection circuit could operate. 11. unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damaged, which could happen due to negative voltage or exce ssive voltage generated during the on and off timing when the inductive load of a motor coil or actuator coils of op tical pick-up is being driven. 12. verify the risks which might be caused by the malfunctions of external comp onents. 13. due to the unshielded structure of this lsi, functions and characteristics of the product cannot be guaranteed under the exposure of light. during normal operation or even under testing condition, please ensure that the lsi is not exposed to light . 14. please ensure that your design does not have metal shield parts touching the chip surface as the surface potential is gnd voltage. 15. pay attention to the breakdown voltage of this lsi when using. more than + 1500 v or less than ? 1500 v electrostatic discharge to all the pins might damage this product. d o c n o . t a4 - ea - 04511 r e v i sio n . 2 e s t a b li s h e d : 2006 - 08 - 29 r e v i s e d : 2013 - 04 - 01
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202

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